[PATCH] D137066: [AMDGPU] Add amdgcn_s_buffer_load_imm intrinsic

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

What's the problem with using a constant offset with the existing intrinsic?



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Comment at: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp:4915
     if (BaseOpcode->AtomicX2) {
+
       Register VData1 = MI.getOperand(3).getReg();
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Extra newline


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  https://reviews.llvm.org/D137066/new/

https://reviews.llvm.org/D137066