[PATCH] D137141: [SDAG] Allow scalable vectors in ComputeNumSignBits

[Philip Reames via Phabricator via llvm-commits]

reames created this revision.
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This is a continuation of the series of patches adding lane wise support for scalable vectors in various knownbit-esq routines.

The basic idea here is that we track a single lane for scalable vectors which corresponds to an unknown number of lanes at runtime. This is enough for us to perform lane wise reasoning on many arithmetic operations.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D137141

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/test/CodeGen/AArch64/sve-masked-gather-legalize.ll
  llvm/test/CodeGen/AArch64/sve-smulo-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll

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