[PATCH] D137141: [SDAG] Allow scalable vectors in ComputeNumSignBits
Philip Reames via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 31 18:25:22 PDT 2022
reames created this revision.
reames added reviewers: frasercrmck, craig.topper, asb, david-arm, paulwalker-arm.
Herald added subscribers: StephenFan, luismarques, apazos, sameer.abuasal, s.egerton, Jim, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, niosHD, sabuasal, bollu, simoncook, johnrusso, rbar, hiraditya, mcrosier.
Herald added a project: All.
reames requested review of this revision.
Herald added subscribers: alextsao1999, pcwang-thead, MaskRay.
Herald added a project: LLVM.
This is a continuation of the series of patches adding lane wise support for scalable vectors in various knownbit-esq routines.
The basic idea here is that we track a single lane for scalable vectors which corresponds to an unknown number of lanes at runtime. This is enough for us to perform lane wise reasoning on many arithmetic operations.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D137141
Files:
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/test/CodeGen/AArch64/sve-masked-gather-legalize.ll
llvm/test/CodeGen/AArch64/sve-smulo-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll
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