[PATCH] D137140: [SDAG] Allow scalable vectors in ComputeKnownBits

[Philip Reames via Phabricator via llvm-commits]

reames created this revision.
reames added reviewers: frasercrmck, craig.topper, asb, paulwalker-arm, david-arm.
Herald added subscribers: foad, StephenFan, arphaman, bollu, hiraditya, mcrosier.
Herald added a project: All.
reames requested review of this revision.
Herald added a subscriber: alextsao1999.
Herald added a project: LLVM.

This is the SelectionDAG equivalent of D136470 <https://reviews.llvm.org/D136470>, and is thus an alternate patch to D128159 <https://reviews.llvm.org/D128159>.

The basic idea here is that we track a single lane for scalable vectors which corresponds to an unknown number of lanes at runtime.  This is enough for us to perform lane wise reasoning on many arithmetic operations.

This patch also includes an implementation for SPLAT_VECTOR as without it, the lane wise reasoning has no base case.  The original patch which inspired this (D128159 <https://reviews.llvm.org/D128159>), also included STEP_VECTOR.  I plan to do that as a separate patch.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D137140

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/test/CodeGen/AArch64/sve-intrinsics-index.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
  llvm/test/CodeGen/AArch64/sve-umulo-sdnode.ll

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