[PATCH] D136999: [AArch64] Lower READCYCLECOUNTER using MRS CNTVCT_EL0

[Salvatore Dipietro via Phabricator via llvm-commits]

salvatoredipietro updated this revision to Diff 472149.
salvatoredipietro added a comment.

Hi Sebastian,
have update the diff removing the predicate for the READCYCLECOUNTER function


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136999/new/

https://reviews.llvm.org/D136999

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/readcyclecounter.ll


Index: llvm/test/CodeGen/AArch64/readcyclecounter.ll
===================================================================
--- llvm/test/CodeGen/AArch64/readcyclecounter.ll
+++ llvm/test/CodeGen/AArch64/readcyclecounter.ll
@@ -1,45 +1,11 @@
-; RUN: llc -mtriple=aarch64-unknown-unknown -mattr=+perfmon -asm-verbose=false < %s |\
-; RUN:   FileCheck %s --check-prefix=CHECK --check-prefix=PERFMON
-; RUN: llc -mtriple=aarch64-unknown-unknown -mattr=-perfmon -asm-verbose=false < %s |\
-; RUN:   FileCheck %s --check-prefix=CHECK --check-prefix=NOPERFMON
-; RUN: llc -mtriple=aarch64-unknown-unknown -mcpu=cortex-a53 -asm-verbose=false < %s |\
-; RUN:   FileCheck %s --check-prefix=CHECK --check-prefix=PERFMON
-; RUN: llc -mtriple=aarch64-unknown-unknown -mcpu=cortex-a55 -asm-verbose=false < %s |\
-; RUN:   FileCheck %s --check-prefix=CHECK --check-prefix=PERFMON
-; RUN: llc -mtriple=aarch64-unknown-unknown -mcpu=cortex-a510 -asm-verbose=false < %s |\
-; RUN:   FileCheck %s --check-prefix=CHECK --check-prefix=PERFMON
-; RUN: llc -mtriple=aarch64-unknown-unknown -mcpu=cortex-a65 -asm-verbose=false < %s |\
-; RUN:   FileCheck %s --check-prefix=CHECK --check-prefix=PERFMON
-; RUN: llc -mtriple=aarch64-unknown-unknown -mcpu=cortex-a76 -asm-verbose=false < %s |\
-; RUN:   FileCheck %s --check-prefix=CHECK --check-prefix=PERFMON
-; RUN: llc -mtriple=aarch64-unknown-unknown -mcpu=cortex-a77 -asm-verbose=false < %s |\
-; RUN:   FileCheck %s --check-prefix=CHECK --check-prefix=PERFMON
-; RUN: llc -mtriple=aarch64-unknown-unknown -mcpu=cortex-a78 -asm-verbose=false < %s |\
-; RUN:   FileCheck %s --check-prefix=CHECK --check-prefix=PERFMON
-; RUN: llc -mtriple=aarch64-unknown-unknown -mcpu=cortex-a78c -asm-verbose=false < %s |\
-; RUN:   FileCheck %s --check-prefix=CHECK --check-prefix=PERFMON
-; RUN: llc -mtriple=aarch64-unknown-unknown -mcpu=cortex-a710 -asm-verbose=false < %s |\
-; RUN:   FileCheck %s --check-prefix=CHECK --check-prefix=PERFMON
-; RUN: llc -mtriple=aarch64-unknown-unknown -mcpu=cortex-r82 -asm-verbose=false < %s |\
-; RUN:   FileCheck %s --check-prefix=CHECK --check-prefix=PERFMON
-; RUN: llc -mtriple=aarch64-unknown-unknown -mcpu=cortex-x1 -asm-verbose=false < %s |\
-; RUN:   FileCheck %s --check-prefix=CHECK --check-prefix=PERFMON
-; RUN: llc -mtriple=aarch64-unknown-unknown -mcpu=cortex-x2 -asm-verbose=false < %s |\
-; RUN:   FileCheck %s --check-prefix=CHECK --check-prefix=PERFMON
-; RUN: llc -mtriple=aarch64-unknown-unknown -mcpu=neoverse-e1 -asm-verbose=false < %s |\
-; RUN:   FileCheck %s --check-prefix=CHECK --check-prefix=PERFMON
-; RUN: llc -mtriple=aarch64-unknown-unknown -mcpu=neoverse-n1 -asm-verbose=false < %s |\
-; RUN:   FileCheck %s --check-prefix=CHECK --check-prefix=PERFMON
-; RUN: llc -mtriple=aarch64-unknown-unknown -mcpu=neoverse-n2 -asm-verbose=false < %s |\
-; RUN:   FileCheck %s --check-prefix=CHECK --check-prefix=PERFMON
-; RUN: llc -mtriple=aarch64-unknown-unknown -mcpu=neoverse-v1 -asm-verbose=false < %s |\
-; RUN:   FileCheck %s --check-prefix=CHECK --check-prefix=PERFMON
+; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
+
 
 define i64 @test_readcyclecounter() nounwind {
   ; CHECK-LABEL:   test_readcyclecounter:
-  ; PERFMON-NEXT:   mrs x0, PMCCNTR_EL0
-  ; NOPERFMON-NEXT: mov x0, xzr
-  ; CHECK-NEXT:     ret
+  ; CHECK:         // %bb.0:
+  ; CHECK-NEXT:    mrs x0, CNTVCT_EL0
+  ; CHECK-NEXT:    ret
   %tmp0 = call i64 @llvm.readcyclecounter()
   ret i64 %tmp0
 }
Index: llvm/lib/Target/AArch64/AArch64InstrInfo.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -114,7 +114,6 @@
                                  AssemblerPredicateWithAll<(all_of FeatureRAS), "ras">;
 def HasRDM           : Predicate<"Subtarget->hasRDM()">,
                                  AssemblerPredicateWithAll<(all_of FeatureRDM), "rdm">;
-def HasPerfMon       : Predicate<"Subtarget->hasPerfMon()">;
 def HasFullFP16      : Predicate<"Subtarget->hasFullFP16()">,
                                  AssemblerPredicateWithAll<(all_of FeatureFullFP16), "fullfp16">;
 def HasFP16FML       : Predicate<"Subtarget->hasFP16FML()">,
@@ -1487,9 +1486,8 @@
   Sched<[]>;
 }
 
-// The cycle counter PMC register is PMCCNTR_EL0.
-let Predicates = [HasPerfMon] in
-def : Pat<(readcyclecounter), (MRS 0xdce8)>;
+// The virtual cycle counter register is CNTVCT_EL0.
+def : Pat<(readcyclecounter), (MRS 0xdf02)>;
 
 // FPCR register
 def : Pat<(i64 (int_aarch64_get_fpcr)), (MRS 0xda20)>;
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -801,10 +801,8 @@
   setOperationAction(ISD::LOAD, MVT::v4f64, Custom);
   setOperationAction(ISD::LOAD, MVT::v4i64, Custom);
 
-  // Lower READCYCLECOUNTER using an mrs from PMCCNTR_EL0.
-  // This requires the Performance Monitors extension.
-  if (Subtarget->hasPerfMon())
-    setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
+  // Lower READCYCLECOUNTER using an mrs from CNTVCT_EL0.
+  setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
 
   if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
       getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {


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