[llvm] 3f532e0 - [test] Add coverage for sign bits and known non-zero for scalable vectors

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2022-10-31T12:03:29-07:00
New Revision: 3f532e0524875c795d849bba69f890abf775a5b6

URL: https://github.com/llvm/llvm-project/commit/3f532e0524875c795d849bba69f890abf775a5b6
DIFF: https://github.com/llvm/llvm-project/commit/3f532e0524875c795d849bba69f890abf775a5b6.diff

LOG: [test] Add coverage for sign bits and known non-zero for scalable vectors

Added: 
    

Modified: 
    llvm/test/Transforms/InstCombine/select.ll

Removed: 
    


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diff  --git a/llvm/test/Transforms/InstCombine/select.ll b/llvm/test/Transforms/InstCombine/select.ll
index 03d3f2347a99..cc72e3579c40 100644
--- a/llvm/test/Transforms/InstCombine/select.ll
+++ b/llvm/test/Transforms/InstCombine/select.ll
@@ -3408,3 +3408,29 @@ define <vscale x 2 x i32> @and_constant_select_svec(<vscale x 2 x i32> %x, <vsca
   %b = select <vscale x 2 x i1> %cond, <vscale x 2 x i32> %a, <vscale x 2 x i32> %x
   ret <vscale x 2 x i32> %b
 }
+
+; TODO: shl should be nsw
+define <vscale x 2 x i32> @scalable_sign_bits(<vscale x 2 x i8> %x) {
+; CHECK-LABEL: @scalable_sign_bits(
+; CHECK-NEXT:    [[A:%.*]] = sext <vscale x 2 x i8> [[X:%.*]] to <vscale x 2 x i32>
+; CHECK-NEXT:    [[B:%.*]] = shl <vscale x 2 x i32> [[A]], shufflevector (<vscale x 2 x i32> insertelement (<vscale x 2 x i32> poison, i32 16, i32 0), <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer)
+; CHECK-NEXT:    ret <vscale x 2 x i32> [[B]]
+;
+  %a = sext <vscale x 2 x i8> %x to <vscale x 2 x i32>
+  %b = shl <vscale x 2 x i32> %a, shufflevector (<vscale x 2 x i32> insertelement (<vscale x 2 x i32> poison, i32 16, i32 0), <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer)
+  ret <vscale x 2 x i32> %b
+}
+
+; TODO: can use ult
+define <vscale x 2 x i1> @scalable_non_zero(<vscale x 2 x i32> %x) {
+; CHECK-LABEL: @scalable_non_zero(
+; CHECK-NEXT:    [[A:%.*]] = or <vscale x 2 x i32> [[X:%.*]], shufflevector (<vscale x 2 x i32> insertelement (<vscale x 2 x i32> poison, i32 1, i32 0), <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer)
+; CHECK-NEXT:    [[B:%.*]] = add nsw <vscale x 2 x i32> [[A]], shufflevector (<vscale x 2 x i32> insertelement (<vscale x 2 x i32> poison, i32 -1, i32 0), <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer)
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ult <vscale x 2 x i32> [[B]], shufflevector (<vscale x 2 x i32> insertelement (<vscale x 2 x i32> poison, i32 56, i32 0), <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer)
+; CHECK-NEXT:    ret <vscale x 2 x i1> [[CMP]]
+;
+  %a = or <vscale x 2 x i32> %x, shufflevector (<vscale x 2 x i32> insertelement (<vscale x 2 x i32> poison, i32 1, i32 0), <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer)
+  %b = add <vscale x 2 x i32> %a, shufflevector (<vscale x 2 x i32> insertelement (<vscale x 2 x i32> poison, i32 -1, i32 0), <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer)
+  %cmp = icmp ult <vscale x 2 x i32> %b, shufflevector (<vscale x 2 x i32> insertelement (<vscale x 2 x i32> poison, i32 56, i32 0), <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer)
+  ret <vscale x 2 x i1> %cmp
+}