[PATCH] D134703: [RISCV][ISel] Refactor the formation of VW operations

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

@qcolombet We're seeing a crash from this in our downstream

  define <vscale x 4 x i64> @test(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1) {    
  entry:                                                                           
    %vp.cast = call <vscale x 4 x i64> @llvm.vp.zext.nxv4i64.nxv4i8(<vscale x 4 x i8> zeroinitializer, <vscale x 4 x i1> %0, i32 1)
    %vp.cast42 = call <vscale x 4 x i64> @llvm.vp.sext.nxv4i64.nxv4i16(<vscale x 4 x i16> zeroinitializer, <vscale x 4 x i1> zeroinitializer, i32 1)
    %vp.op = call <vscale x 4 x i64> @llvm.vp.add.nxv4i64(<vscale x 4 x i64> %vp.cast42, <vscale x 4 x i64> %vp.cast, <vscale x 4 x i1> %0, i32 1)
    ret <vscale x 4 x i64> %vp.op                                                  
  }                                                                                
                                                                                   
  declare <vscale x 4 x i64> @llvm.vp.zext.nxv4i64.nxv4i8(<vscale x 4 x i8>, <vscale x 4 x i1>, i32)
  declare <vscale x 4 x i64> @llvm.vp.sext.nxv4i64.nxv4i16(<vscale x 4 x i16>, <vscale x 4 x i1>, i32)
  declare <vscale x 4 x i64> @llvm.vp.add.nxv4i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i1>, i32)

We end up with this

  Vector/type-legalized selection DAG: %bb.0 'test:entry'                          
  SelectionDAG has 15 nodes:                                                       
    t0: ch,glue = EntryToken                                                       
    t2: nxv4i1,ch = CopyFromReg t0, Register:nxv4i1 %0                             
          t12: nxv4i16 = splat_vector Constant:i64<0>                              
          t14: nxv4i1 = splat_vector Constant:i64<0>                               
        t23: nxv4i64 = RISCVISD::VSEXT_VL t12, t14, Constant:i64<1>                
          t7: nxv4i8 = splat_vector Constant:i64<0>                                
        t22: nxv4i64 = RISCVISD::VZEXT_VL t7, t2, Constant:i64<1>                  
      t25: nxv4i64 = RISCVISD::ADD_VL t23, t22, undef:nxv4i64, t2, Constant:i64<1> 
    t19: ch,glue = CopyToReg t0, Register:nxv4i64 $v8m4, t25                       
    t20: ch = RISCVISD::RET_FLAG t19, Register:nxv4i64 $v8m4, t19:1                
                                                                                   
                                                                                   
                                                                                   
  Combining: t25: nxv4i64 = RISCVISD::ADD_VL t23, t22, undef:nxv4i64, t2, Constant:i64<1>
  Creating new node: t26: nxv4i32 = RISCVISD::VZEXT_VL t7, t2, Constant:i64<1>     
  Creating new node: t27: nxv4i64 = RISCVISD::VWADDU_W_VL t12, t26, undef:nxv4i64, t2, Constant:i64<1>
   ... into: t27: nxv4i64 = RISCVISD::VWADDU_W_VL t12, t26, undef:nxv4i64, t2, Constant:i64<1>

The first operand to the VWADDU_W_VL has type nxv4i16 instead of the nxv4i64 it should have. We appear to have dropped the original VSEXT_VL.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D134703/new/

https://reviews.llvm.org/D134703