[PATCH] D136675: [MachineCSE] Allow PRE of instructions that read physical registers

[John Brawn via Phabricator via llvm-commits]

john.brawn updated this revision to Diff 472023.
john.brawn added a comment.

Adjusted to find physical register uses and defs by iterating through all operands, as the defs list doesn't include implicit defs. Added a test based on the code in ffmpeg that was getting incorrectly optimised.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136675/new/

https://reviews.llvm.org/D136675

Files:
  llvm/lib/CodeGen/MachineCSE.cpp
  llvm/test/CodeGen/AMDGPU/GlobalISel/hip.extern.shared.array.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
  llvm/test/CodeGen/AMDGPU/selectcc-opt.ll
  llvm/test/CodeGen/ARM/machine-cse-cmp.ll
  llvm/test/CodeGen/PowerPC/machine-cse-rm-pre.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/memcall.ll

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