[PATCH] D136747: [AArch64][SVE2] Add the SVE2.1 cntp instruction

David Sherwood via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Oct 31 08:04:54 PDT 2022


david-arm marked 2 inline comments as done.
david-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64RegisterInfo.td:923
+    : PPRRegOp<Suffix, C, ElementSizeNone, RC> {
+  let PrintMethod = "printPredicateAsCounter<" # EltSize # ">";
+}
----------------
paulwalker-arm wrote:
> Do you need a special PrintMethod here? I likely missed this be reviewing your other patch but `printSVERegOp` (i.e. the default action for `PPRRegOp`) looks like it might just work.
Sadly it doesn't work because it prints out "p8" instead of "pn8", for example. The registers alias and so the function `getRegisterName` just returns "p8".


================
Comment at: llvm/lib/Target/AArch64/AArch64SystemOperands.td:320
+
+class SVEPREDCNTPAT<string name, bits<1> encoding> : SearchableTable {
+  let SearchableFields = ["Name", "Encoding"];
----------------
paulwalker-arm wrote:
> Perhaps I'm being picky but I don't see this as a predicate pattern.  It's really a vector length specifier.
OK, I'm a bit short of ideas. :) How about SVEVECLENMUL?


================
Comment at: llvm/lib/Target/AArch64/AArch64SystemOperands.td:325
+  string Name = name;
+  bits<1> Encoding;
+  let Encoding = encoding;
----------------
paulwalker-arm wrote:
> FYI: `bit` would work here also.
I actually tried that already as I thought the same as you, but it wouldn't compile. Here is the error:

```AArch64SystemOperands.td:326:7: error: In table 'SVEPREDCNTPATsList' lookup method 'lookupSVEPREDCNTPATByEncoding', key field 'Encoding' has invalid type: bit
  let Encoding = encoding;```


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136747/new/

https://reviews.llvm.org/D136747



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