[llvm] 4b48c39 - [AArch64][SVE2] Add the SVE2.1 shift-and-narrow instructions
David Sherwood via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 31 06:46:03 PDT 2022
Author: David Sherwood
Date: 2022-10-31T13:45:57Z
New Revision: 4b48c3993be08f1a330dfb91def82baf6efdb544
URL: https://github.com/llvm/llvm-project/commit/4b48c3993be08f1a330dfb91def82baf6efdb544
DIFF: https://github.com/llvm/llvm-project/commit/4b48c3993be08f1a330dfb91def82baf6efdb544.diff
LOG: [AArch64][SVE2] Add the SVE2.1 shift-and-narrow instructions
This patch adds the assembly/disassembly for the following instructions:
sqrshrn : Signed saturating rounding shift right narrow by immediate and interleave
sqrshrun : Signed saturating rounding shift right unsigned narrow by immediate and interleave
uqrshrn : Unsigned saturating rounding shift right narrow by immediate and interleave
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09
Differential Revision: https://reviews.llvm.org/D136690
Added:
llvm/test/MC/AArch64/SVE2p1/sqrshrn-diagnostics.s
llvm/test/MC/AArch64/SVE2p1/sqrshrn.s
llvm/test/MC/AArch64/SVE2p1/sqrshrun-diagnostics.s
llvm/test/MC/AArch64/SVE2p1/sqrshrun.s
llvm/test/MC/AArch64/SVE2p1/uqrshrn-diagnostics.s
llvm/test/MC/AArch64/SVE2p1/uqrshrn.s
Modified:
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/lib/Target/AArch64/SVEInstrFormats.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 14bc9edcadd32..9db47006b7858 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -3595,4 +3595,7 @@ defm PTRUE_C : sve2p1_ptrue_pn<"ptrue">;
defm SQCVTN_Z2Z_StoH : sve2p1_multi_vec_extract_narrow<"sqcvtn", 0b00>;
defm UQCVTN_Z2Z_StoH : sve2p1_multi_vec_extract_narrow<"uqcvtn", 0b01>;
defm SQCVTUN_Z2Z_StoH : sve2p1_multi_vec_extract_narrow<"sqcvtun", 0b10>;
+defm SQRSHRN_Z2ZI_StoH : sve2p1_multi_vec_shift_narrow<"sqrshrn", 0b101>;
+defm UQRSHRN_Z2ZI_StoH : sve2p1_multi_vec_shift_narrow<"uqrshrn", 0b111>;
+defm SQRSHRUN_Z2ZI_StoH : sve2p1_multi_vec_shift_narrow<"sqrshrun", 0b001>;
} // End HasSVE2p1_or_HasSME2
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index 76a79d2abd5a7..2eb1a9e4d264b 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -8763,3 +8763,28 @@ class sve2p1_multi_vec_extract_narrow<string mnemonic, bits<2> opc, bits<3> tsz>
multiclass sve2p1_multi_vec_extract_narrow<string mnemonic, bits<2> opc> {
def : sve2p1_multi_vec_extract_narrow<mnemonic, opc, 0b010>;
}
+
+// SVE2 multi-vec shift narrow
+class sve2p1_multi_vec_shift_narrow<string mnemonic, bits<3> opc, bits<2> tsz>
+ : I<(outs ZPR16:$Zd), (ins ZZ_s_mul_r:$Zn, vecshiftR16:$imm4),
+ mnemonic, "\t$Zd, $Zn, $imm4",
+ "", []>, Sched<[]> {
+ bits<5> Zd;
+ bits<4> Zn;
+ bits<4> imm4;
+ let Inst{31-23} = 0b010001011;
+ let Inst{22} = tsz{1};
+ let Inst{21} = 0b1;
+ let Inst{20} = tsz{0};
+ let Inst{19-16} = imm4;
+ let Inst{15-14} = 0b00;
+ let Inst{13-11} = opc;
+ let Inst{10} = 0b0;
+ let Inst{9-6} = Zn;
+ let Inst{5} = 0b0;
+ let Inst{4-0} = Zd;
+}
+
+multiclass sve2p1_multi_vec_shift_narrow<string mnemonic, bits<3> opc> {
+ def : sve2p1_multi_vec_shift_narrow<mnemonic, opc, 0b01>;
+}
diff --git a/llvm/test/MC/AArch64/SVE2p1/sqrshrn-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/sqrshrn-diagnostics.s
new file mode 100644
index 0000000000000..a8972acf4b346
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/sqrshrn-diagnostics.s
@@ -0,0 +1,40 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+sqrshrn z0.h, {z0.s-z2.s}, #16
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: sqrshrn z0.h, {z0.s-z2.s}, #16
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqrshrn z0.h, {z1.s-z2.s}, #16
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: sqrshrn z0.h, {z1.s-z2.s}, #16
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector suffixes
+
+sqrshrn z0.b, {z0.s-z1.s}, #16
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sqrshrn z0.b, {z0.s-z1.s}, #16
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqrshrn z0.h, {z0.d-z1.d}, #16
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: sqrshrn z0.h, {z0.d-z1.d}, #16
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid immediate
+
+sqrshrn z0.h, {z0.s-z1.s}, #17
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16].
+// CHECK-NEXT: sqrshrn z0.h, {z0.s-z1.s}, #17
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqrshrn z0.h, {z0.s-z1.s}, #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16].
+// CHECK-NEXT: sqrshrn z0.h, {z0.s-z1.s}, #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/sqrshrn.s b/llvm/test/MC/AArch64/SVE2p1/sqrshrn.s
new file mode 100644
index 0000000000000..1ee4e7aa75da9
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/sqrshrn.s
@@ -0,0 +1,38 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+sqrshrn z0.h, {z0.s-z1.s}, #16 // 01000101-10110000-00101000-00000000
+// CHECK-INST: sqrshrn z0.h, { z0.s, z1.s }, #16
+// CHECK-ENCODING: [0x00,0x28,0xb0,0x45]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 45b02800 <unknown>
+
+sqrshrn z21.h, {z10.s-z11.s}, #11 // 01000101-10110101-00101001-01010101
+// CHECK-INST: sqrshrn z21.h, { z10.s, z11.s }, #11
+// CHECK-ENCODING: [0x55,0x29,0xb5,0x45]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 45b52955 <unknown>
+
+sqrshrn z23.h, {z12.s-z13.s}, #8 // 01000101-10111000-00101001-10010111
+// CHECK-INST: sqrshrn z23.h, { z12.s, z13.s }, #8
+// CHECK-ENCODING: [0x97,0x29,0xb8,0x45]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 45b82997 <unknown>
+
+sqrshrn z31.h, {z30.s-z31.s}, #1 // 01000101-10111111-00101011-11011111
+// CHECK-INST: sqrshrn z31.h, { z30.s, z31.s }, #1
+// CHECK-ENCODING: [0xdf,0x2b,0xbf,0x45]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 45bf2bdf <unknown>
diff --git a/llvm/test/MC/AArch64/SVE2p1/sqrshrun-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/sqrshrun-diagnostics.s
new file mode 100644
index 0000000000000..e3fcade376b73
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/sqrshrun-diagnostics.s
@@ -0,0 +1,40 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+sqrshrun z0.h, {z0.s-z2.s}, #16
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: sqrshrun z0.h, {z0.s-z2.s}, #16
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqrshrun z0.h, {z1.s-z2.s}, #16
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: sqrshrun z0.h, {z1.s-z2.s}, #16
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector suffixes
+
+sqrshrun z0.b, {z0.s-z1.s}, #16
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sqrshrun z0.b, {z0.s-z1.s}, #16
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqrshrun z0.h, {z0.d-z1.d}, #16
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: sqrshrun z0.h, {z0.d-z1.d}, #16
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid immediate
+
+sqrshrun z0.h, {z0.s-z1.s}, #17
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16].
+// CHECK-NEXT: sqrshrun z0.h, {z0.s-z1.s}, #17
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqrshrun z0.h, {z0.s-z1.s}, #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16].
+// CHECK-NEXT: sqrshrun z0.h, {z0.s-z1.s}, #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/sqrshrun.s b/llvm/test/MC/AArch64/SVE2p1/sqrshrun.s
new file mode 100644
index 0000000000000..ba47e02e297ff
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/sqrshrun.s
@@ -0,0 +1,38 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+sqrshrun z0.h, {z0.s-z1.s}, #16 // 01000101-10110000-00001000-00000000
+// CHECK-INST: sqrshrun z0.h, { z0.s, z1.s }, #16
+// CHECK-ENCODING: [0x00,0x08,0xb0,0x45]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 45b00800 <unknown>
+
+sqrshrun z21.h, {z10.s-z11.s}, #11 // 01000101-10110101-00001001-01010101
+// CHECK-INST: sqrshrun z21.h, { z10.s, z11.s }, #11
+// CHECK-ENCODING: [0x55,0x09,0xb5,0x45]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 45b50955 <unknown>
+
+sqrshrun z23.h, {z12.s-z13.s}, #8 // 01000101-10111000-00001001-10010111
+// CHECK-INST: sqrshrun z23.h, { z12.s, z13.s }, #8
+// CHECK-ENCODING: [0x97,0x09,0xb8,0x45]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 45b80997 <unknown>
+
+sqrshrun z31.h, {z30.s-z31.s}, #1 // 01000101-10111111-00001011-11011111
+// CHECK-INST: sqrshrun z31.h, { z30.s, z31.s }, #1
+// CHECK-ENCODING: [0xdf,0x0b,0xbf,0x45]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 45bf0bdf <unknown>
diff --git a/llvm/test/MC/AArch64/SVE2p1/uqrshrn-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/uqrshrn-diagnostics.s
new file mode 100644
index 0000000000000..cb7261c26365d
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/uqrshrn-diagnostics.s
@@ -0,0 +1,40 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+uqrshrn z0.h, {z0.s-z2.s}, #16
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: uqrshrn z0.h, {z0.s-z2.s}, #16
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqrshrn z0.h, {z1.s-z2.s}, #16
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: uqrshrn z0.h, {z1.s-z2.s}, #16
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector suffixes
+
+uqrshrn z0.b, {z0.s-z1.s}, #16
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: uqrshrn z0.b, {z0.s-z1.s}, #16
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqrshrn z0.h, {z0.d-z1.d}, #16
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: uqrshrn z0.h, {z0.d-z1.d}, #16
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid immediate
+
+uqrshrn z0.h, {z0.s-z1.s}, #17
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16].
+// CHECK-NEXT: uqrshrn z0.h, {z0.s-z1.s}, #17
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqrshrn z0.h, {z0.s-z1.s}, #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16].
+// CHECK-NEXT: uqrshrn z0.h, {z0.s-z1.s}, #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/uqrshrn.s b/llvm/test/MC/AArch64/SVE2p1/uqrshrn.s
new file mode 100644
index 0000000000000..b68223edc5169
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/uqrshrn.s
@@ -0,0 +1,38 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+uqrshrn z0.h, {z0.s-z1.s}, #16 // 01000101-10110000-00111000-00000000
+// CHECK-INST: uqrshrn z0.h, { z0.s, z1.s }, #16
+// CHECK-ENCODING: [0x00,0x38,0xb0,0x45]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 45b03800 <unknown>
+
+uqrshrn z21.h, {z10.s-z11.s}, #11 // 01000101-10110101-00111001-01010101
+// CHECK-INST: uqrshrn z21.h, { z10.s, z11.s }, #11
+// CHECK-ENCODING: [0x55,0x39,0xb5,0x45]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 45b53955 <unknown>
+
+uqrshrn z23.h, {z12.s-z13.s}, #8 // 01000101-10111000-00111001-10010111
+// CHECK-INST: uqrshrn z23.h, { z12.s, z13.s }, #8
+// CHECK-ENCODING: [0x97,0x39,0xb8,0x45]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 45b83997 <unknown>
+
+uqrshrn z31.h, {z30.s-z31.s}, #1 // 01000101-10111111-00111011-11011111
+// CHECK-INST: uqrshrn z31.h, { z30.s, z31.s }, #1
+// CHECK-ENCODING: [0xdf,0x3b,0xbf,0x45]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 45bf3bdf <unknown>
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