[PATCH] D136150: [AArch64]SME2 Single and Multi vector Shift and Multiply instructions

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:3574
+// SME2 multi-vec saturating shift right narrow
+class sme2_sat_shift_vector_vg2<string mnemonic, bit op, bit u>
+    : I<(outs ZPR16:$Zd), (ins ZZ_s_mul_r:$Zn, vecshiftR16:$imm4),
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Can you create a multiclass for this that means the instructions get an element type suffix? Either that or just add the suffix to the instruction name, but I think we'll need a multiclass anyway for when we wire in code generation support.


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Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:3598-3600
+  let Inst{31-24} = 0b11000001;
+  let Inst{21}    = 0b1;
+  let Inst{15-11} = 0b11011;
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Please see `sve_int_bin_pred_shift_imm_left` for how we usually handle variable length shift imm fields.  Following that idiom `sme2_sat_shift_vector_vg4` will match the encoding group (i.e. include entries for `tsize` and `imm5`) with the multiclass passing in the fixed parts and the fills in the rest using the `imm` of the required bit length for its datatype.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136150/new/

https://reviews.llvm.org/D136150