[PATCH] D136999: [AArch64] Lower READCYCLECOUNTER using MRS CNTVCT_EL0

[Salvatore Dipietro via Phabricator via llvm-commits]

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As suggested in D12425 <https://reviews.llvm.org/D12425> it would be better for the readcyclecounter function on ARM architecture to use the CNTVCT_EL0 register (Counter-timer Virtual Count register) instead of the PMCCNTR_EL0 (Performance Monitors Cycle Count Register) because the PMCCNTR_EL0 is a PMU register which, depending on the configuration, it might always return zeroes and it doesn't guaranteed to always be increased.


https://reviews.llvm.org/D136999

Files:
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/readcyclecounter.ll


Index: llvm/test/CodeGen/AArch64/readcyclecounter.ll
===================================================================
--- llvm/test/CodeGen/AArch64/readcyclecounter.ll
+++ llvm/test/CodeGen/AArch64/readcyclecounter.ll
@@ -37,7 +37,7 @@
 
 define i64 @test_readcyclecounter() nounwind {
   ; CHECK-LABEL:   test_readcyclecounter:
-  ; PERFMON-NEXT:   mrs x0, PMCCNTR_EL0
+  ; PERFMON-NEXT:   mrs x0, CNTVCT_EL0
   ; NOPERFMON-NEXT: mov x0, xzr
   ; CHECK-NEXT:     ret
   %tmp0 = call i64 @llvm.readcyclecounter()
Index: llvm/lib/Target/AArch64/AArch64InstrInfo.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -1487,9 +1487,9 @@
   Sched<[]>;
 }
 
-// The cycle counter PMC register is PMCCNTR_EL0.
+// The virtual cycle counter register is CNTVCT_EL0.
 let Predicates = [HasPerfMon] in
-def : Pat<(readcyclecounter), (MRS 0xdce8)>;
+def : Pat<(readcyclecounter), (MRS 0xdf02)>;
 
 // FPCR register
 def : Pat<(i64 (int_aarch64_get_fpcr)), (MRS 0xda20)>;


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