[llvm] 1d4a57b - [RISCV] Merge WriteLDW and WriteLDWU schedule classes.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-10-28T11:57:33-07:00
New Revision: 1d4a57bd12783ff98faed630e800e2c3675dd4d6

URL: https://github.com/llvm/llvm-project/commit/1d4a57bd12783ff98faed630e800e2c3675dd4d6
DIFF: https://github.com/llvm/llvm-project/commit/1d4a57bd12783ff98faed630e800e2c3675dd4d6.diff

LOG: [RISCV] Merge WriteLDW and WriteLDWU schedule classes.

We don't distinquish signed vs unsigned for B and H loads.

Maybe this split was because LDWU isn't in RV32I? I don't think
that distinction matters to the scheduler. If your processor
only supports RV32I then having LWU in the SchedClass doesn't matter.
If your target supports RV64I, then LW and LWU are likely the same.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.td
    llvm/lib/Target/RISCV/RISCVSchedRocket.td
    llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    llvm/lib/Target/RISCV/RISCVSchedule.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 12bd105053e7..ebf3113497b9 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -740,7 +740,7 @@ def CSRRCI : CSR_ii<0b111, "csrrci">;
 /// RV64I instructions
 
 let Predicates = [IsRV64] in {
-def LWU   : Load_ri<0b110, "lwu">, Sched<[WriteLDWU, ReadMemBase]>;
+def LWU   : Load_ri<0b110, "lwu">, Sched<[WriteLDW, ReadMemBase]>;
 def LD    : Load_ri<0b011, "ld">, Sched<[WriteLDD, ReadMemBase]>;
 def SD    : Store_rri<0b011, "sd">, Sched<[WriteSTD, ReadStoreData, ReadMemBase]>;
 

diff  --git a/llvm/lib/Target/RISCV/RISCVSchedRocket.td b/llvm/lib/Target/RISCV/RISCVSchedRocket.td
index e39585ff0841..ed0e9f2eeca9 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedRocket.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedRocket.td
@@ -93,7 +93,6 @@ def : WriteRes<WriteLDH, [RocketUnitMem]>;
 
 let Latency = 2 in {
 def : WriteRes<WriteLDW, [RocketUnitMem]>;
-def : WriteRes<WriteLDWU, [RocketUnitMem]>;
 def : WriteRes<WriteLDD, [RocketUnitMem]>;
 def : WriteRes<WriteFLD32, [RocketUnitMem]>;
 def : WriteRes<WriteFLD64, [RocketUnitMem]>;

diff  --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index 17df9e212eb8..329209f8aa81 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -88,7 +88,6 @@ let Latency = 3 in {
 def : WriteRes<WriteLDB, [SiFive7PipeA]>;
 def : WriteRes<WriteLDH, [SiFive7PipeA]>;
 def : WriteRes<WriteLDW, [SiFive7PipeA]>;
-def : WriteRes<WriteLDWU, [SiFive7PipeA]>;
 def : WriteRes<WriteLDD, [SiFive7PipeA]>;
 }
 

diff  --git a/llvm/lib/Target/RISCV/RISCVSchedule.td b/llvm/lib/Target/RISCV/RISCVSchedule.td
index 0437f78c3daf..41c74b261c5a 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedule.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedule.td
@@ -25,7 +25,6 @@ def WriteNop        : SchedWrite;
 def WriteLDB        : SchedWrite;    // Load byte
 def WriteLDH        : SchedWrite;    // Load half-word
 def WriteLDW        : SchedWrite;    // Load word
-def WriteLDWU       : SchedWrite;    // Load word unsigned
 def WriteLDD        : SchedWrite;    // Load double-word
 def WriteCSR        : SchedWrite;    // CSR instructions
 def WriteSTB        : SchedWrite;    // Store byte