[PATCH] D136091: [AArch64] SME2 multi-vec unpack and ZIP two and four registers

[Caroline via Phabricator via llvm-commits]

CarolineConcatto added inline comments.


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Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:1820
 
-class sme2_fp_cvt_vg4_multi<string mnemonic, bits<3> op>
-    : I<(outs ZZZZ_s_mul_r:$Zd), (ins ZZZZ_s_mul_r:$Zn),
+class sme2_zip_cvt_vg4_multi<bits<2> sz, bits<2> op1, bits<3> op2,
+                             bit op3, RegisterOperand first_vector_ty,
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paulwalker-arm wrote:
> paulwalker-arm wrote:
> > Have you reached the point where this class can just represent `SME2 Multi-vector - SVE Constructive Unary`?  Perhaps not all instructions within that encoding group fit but looking at this new definition of `Inst`, which I very much like by the way, suggests that is what this class effectively represents. So you just need to change a few opcodes to match the documentation.
> Actually looking at the register layouts perhaps this is not quite so clear cut, but I do think it's worth investigating to see if there's an options for more reuse.  If you decide the current class is still the best route then I do think streaming the opcode across three variables is not great.
I looked before trying to merge them, but the registers sizes change between the group of instructions.

I reduced from 4 to 3 set of bit. The problem is that for cvt we need 3 bits to select the instructions, and for zip it doesn't, the same 3 bits  need to be set because they are also the size.


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  https://reviews.llvm.org/D136091/new/

https://reviews.llvm.org/D136091