[llvm] ea1a2aa - [RISCV] Map pseudos to their BaseInstr to reduce cases
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 28 08:58:02 PDT 2022
This is a great cleanup. Thanks for doing it.
Philip
On 10/27/22 01:50, via llvm-commits wrote:
> Author: wangpc
> Date: 2022-10-27T16:50:15+08:00
> New Revision: ea1a2aaa9ad39fb79de2de7d753374bc0a44e7ba
>
> URL: https://github.com/llvm/llvm-project/commit/ea1a2aaa9ad39fb79de2de7d753374bc0a44e7ba
> DIFF: https://github.com/llvm/llvm-project/commit/ea1a2aaa9ad39fb79de2de7d753374bc0a44e7ba.diff
>
> LOG: [RISCV] Map pseudos to their BaseInstr to reduce cases
>
> There are a lot of cases for pseudos of the same instruction, here
> we just use existed mapping table to map pseudos to real instructions
> to reduce cases.
>
> Reviewed By: kito-cheng
>
> Differential Revision: https://reviews.llvm.org/D128271
>
> Added:
>
>
> Modified:
> llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
>
> Removed:
>
>
>
> ################################################################################
> diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
> index b0341620e788..9b903462728a 100644
> --- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
> +++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
> @@ -67,32 +67,20 @@ static bool isVLPreservingConfig(const MachineInstr &MI) {
> return RISCV::X0 == MI.getOperand(0).getReg();
> }
>
> +static uint16_t getRVVMCOpcode(uint16_t RVVPseudoOpcode) {
> + const RISCVVPseudosTable::PseudoInfo *RVV =
> + RISCVVPseudosTable::getPseudoInfo(RVVPseudoOpcode);
> + if (!RVV)
> + return 0;
> + return RVV->BaseInstr;
> +}
> +
> static bool isScalarMoveInstr(const MachineInstr &MI) {
> - switch (MI.getOpcode()) {
> + switch (getRVVMCOpcode(MI.getOpcode())) {
> default:
> return false;
> - case RISCV::PseudoVMV_S_X_M1:
> - case RISCV::PseudoVMV_S_X_M2:
> - case RISCV::PseudoVMV_S_X_M4:
> - case RISCV::PseudoVMV_S_X_M8:
> - case RISCV::PseudoVMV_S_X_MF2:
> - case RISCV::PseudoVMV_S_X_MF4:
> - case RISCV::PseudoVMV_S_X_MF8:
> - case RISCV::PseudoVFMV_S_F16_M1:
> - case RISCV::PseudoVFMV_S_F16_M2:
> - case RISCV::PseudoVFMV_S_F16_M4:
> - case RISCV::PseudoVFMV_S_F16_M8:
> - case RISCV::PseudoVFMV_S_F16_MF2:
> - case RISCV::PseudoVFMV_S_F16_MF4:
> - case RISCV::PseudoVFMV_S_F32_M1:
> - case RISCV::PseudoVFMV_S_F32_M2:
> - case RISCV::PseudoVFMV_S_F32_M4:
> - case RISCV::PseudoVFMV_S_F32_M8:
> - case RISCV::PseudoVFMV_S_F32_MF2:
> - case RISCV::PseudoVFMV_S_F64_M1:
> - case RISCV::PseudoVFMV_S_F64_M2:
> - case RISCV::PseudoVFMV_S_F64_M4:
> - case RISCV::PseudoVFMV_S_F64_M8:
> + case RISCV::VMV_S_X:
> + case RISCV::VFMV_S_F:
> return true;
> }
> }
> @@ -100,188 +88,28 @@ static bool isScalarMoveInstr(const MachineInstr &MI) {
> /// Get the EEW for a load or store instruction. Return None if MI is not
> /// a load or store which ignores SEW.
> static Optional<unsigned> getEEWForLoadStore(const MachineInstr &MI) {
> - switch (MI.getOpcode()) {
> + switch (getRVVMCOpcode(MI.getOpcode())) {
> default:
> return None;
> - case RISCV::PseudoVLE8_V_M1:
> - case RISCV::PseudoVLE8_V_M1_MASK:
> - case RISCV::PseudoVLE8_V_M2:
> - case RISCV::PseudoVLE8_V_M2_MASK:
> - case RISCV::PseudoVLE8_V_M4:
> - case RISCV::PseudoVLE8_V_M4_MASK:
> - case RISCV::PseudoVLE8_V_M8:
> - case RISCV::PseudoVLE8_V_M8_MASK:
> - case RISCV::PseudoVLE8_V_MF2:
> - case RISCV::PseudoVLE8_V_MF2_MASK:
> - case RISCV::PseudoVLE8_V_MF4:
> - case RISCV::PseudoVLE8_V_MF4_MASK:
> - case RISCV::PseudoVLE8_V_MF8:
> - case RISCV::PseudoVLE8_V_MF8_MASK:
> - case RISCV::PseudoVLSE8_V_M1:
> - case RISCV::PseudoVLSE8_V_M1_MASK:
> - case RISCV::PseudoVLSE8_V_M2:
> - case RISCV::PseudoVLSE8_V_M2_MASK:
> - case RISCV::PseudoVLSE8_V_M4:
> - case RISCV::PseudoVLSE8_V_M4_MASK:
> - case RISCV::PseudoVLSE8_V_M8:
> - case RISCV::PseudoVLSE8_V_M8_MASK:
> - case RISCV::PseudoVLSE8_V_MF2:
> - case RISCV::PseudoVLSE8_V_MF2_MASK:
> - case RISCV::PseudoVLSE8_V_MF4:
> - case RISCV::PseudoVLSE8_V_MF4_MASK:
> - case RISCV::PseudoVLSE8_V_MF8:
> - case RISCV::PseudoVLSE8_V_MF8_MASK:
> - case RISCV::PseudoVSE8_V_M1:
> - case RISCV::PseudoVSE8_V_M1_MASK:
> - case RISCV::PseudoVSE8_V_M2:
> - case RISCV::PseudoVSE8_V_M2_MASK:
> - case RISCV::PseudoVSE8_V_M4:
> - case RISCV::PseudoVSE8_V_M4_MASK:
> - case RISCV::PseudoVSE8_V_M8:
> - case RISCV::PseudoVSE8_V_M8_MASK:
> - case RISCV::PseudoVSE8_V_MF2:
> - case RISCV::PseudoVSE8_V_MF2_MASK:
> - case RISCV::PseudoVSE8_V_MF4:
> - case RISCV::PseudoVSE8_V_MF4_MASK:
> - case RISCV::PseudoVSE8_V_MF8:
> - case RISCV::PseudoVSE8_V_MF8_MASK:
> - case RISCV::PseudoVSSE8_V_M1:
> - case RISCV::PseudoVSSE8_V_M1_MASK:
> - case RISCV::PseudoVSSE8_V_M2:
> - case RISCV::PseudoVSSE8_V_M2_MASK:
> - case RISCV::PseudoVSSE8_V_M4:
> - case RISCV::PseudoVSSE8_V_M4_MASK:
> - case RISCV::PseudoVSSE8_V_M8:
> - case RISCV::PseudoVSSE8_V_M8_MASK:
> - case RISCV::PseudoVSSE8_V_MF2:
> - case RISCV::PseudoVSSE8_V_MF2_MASK:
> - case RISCV::PseudoVSSE8_V_MF4:
> - case RISCV::PseudoVSSE8_V_MF4_MASK:
> - case RISCV::PseudoVSSE8_V_MF8:
> - case RISCV::PseudoVSSE8_V_MF8_MASK:
> + case RISCV::VLE8_V:
> + case RISCV::VLSE8_V:
> + case RISCV::VSE8_V:
> + case RISCV::VSSE8_V:
> return 8;
> - case RISCV::PseudoVLE16_V_M1:
> - case RISCV::PseudoVLE16_V_M1_MASK:
> - case RISCV::PseudoVLE16_V_M2:
> - case RISCV::PseudoVLE16_V_M2_MASK:
> - case RISCV::PseudoVLE16_V_M4:
> - case RISCV::PseudoVLE16_V_M4_MASK:
> - case RISCV::PseudoVLE16_V_M8:
> - case RISCV::PseudoVLE16_V_M8_MASK:
> - case RISCV::PseudoVLE16_V_MF2:
> - case RISCV::PseudoVLE16_V_MF2_MASK:
> - case RISCV::PseudoVLE16_V_MF4:
> - case RISCV::PseudoVLE16_V_MF4_MASK:
> - case RISCV::PseudoVLSE16_V_M1:
> - case RISCV::PseudoVLSE16_V_M1_MASK:
> - case RISCV::PseudoVLSE16_V_M2:
> - case RISCV::PseudoVLSE16_V_M2_MASK:
> - case RISCV::PseudoVLSE16_V_M4:
> - case RISCV::PseudoVLSE16_V_M4_MASK:
> - case RISCV::PseudoVLSE16_V_M8:
> - case RISCV::PseudoVLSE16_V_M8_MASK:
> - case RISCV::PseudoVLSE16_V_MF2:
> - case RISCV::PseudoVLSE16_V_MF2_MASK:
> - case RISCV::PseudoVLSE16_V_MF4:
> - case RISCV::PseudoVLSE16_V_MF4_MASK:
> - case RISCV::PseudoVSE16_V_M1:
> - case RISCV::PseudoVSE16_V_M1_MASK:
> - case RISCV::PseudoVSE16_V_M2:
> - case RISCV::PseudoVSE16_V_M2_MASK:
> - case RISCV::PseudoVSE16_V_M4:
> - case RISCV::PseudoVSE16_V_M4_MASK:
> - case RISCV::PseudoVSE16_V_M8:
> - case RISCV::PseudoVSE16_V_M8_MASK:
> - case RISCV::PseudoVSE16_V_MF2:
> - case RISCV::PseudoVSE16_V_MF2_MASK:
> - case RISCV::PseudoVSE16_V_MF4:
> - case RISCV::PseudoVSE16_V_MF4_MASK:
> - case RISCV::PseudoVSSE16_V_M1:
> - case RISCV::PseudoVSSE16_V_M1_MASK:
> - case RISCV::PseudoVSSE16_V_M2:
> - case RISCV::PseudoVSSE16_V_M2_MASK:
> - case RISCV::PseudoVSSE16_V_M4:
> - case RISCV::PseudoVSSE16_V_M4_MASK:
> - case RISCV::PseudoVSSE16_V_M8:
> - case RISCV::PseudoVSSE16_V_M8_MASK:
> - case RISCV::PseudoVSSE16_V_MF2:
> - case RISCV::PseudoVSSE16_V_MF2_MASK:
> - case RISCV::PseudoVSSE16_V_MF4:
> - case RISCV::PseudoVSSE16_V_MF4_MASK:
> + case RISCV::VLE16_V:
> + case RISCV::VLSE16_V:
> + case RISCV::VSE16_V:
> + case RISCV::VSSE16_V:
> return 16;
> - case RISCV::PseudoVLE32_V_M1:
> - case RISCV::PseudoVLE32_V_M1_MASK:
> - case RISCV::PseudoVLE32_V_M2:
> - case RISCV::PseudoVLE32_V_M2_MASK:
> - case RISCV::PseudoVLE32_V_M4:
> - case RISCV::PseudoVLE32_V_M4_MASK:
> - case RISCV::PseudoVLE32_V_M8:
> - case RISCV::PseudoVLE32_V_M8_MASK:
> - case RISCV::PseudoVLE32_V_MF2:
> - case RISCV::PseudoVLE32_V_MF2_MASK:
> - case RISCV::PseudoVLSE32_V_M1:
> - case RISCV::PseudoVLSE32_V_M1_MASK:
> - case RISCV::PseudoVLSE32_V_M2:
> - case RISCV::PseudoVLSE32_V_M2_MASK:
> - case RISCV::PseudoVLSE32_V_M4:
> - case RISCV::PseudoVLSE32_V_M4_MASK:
> - case RISCV::PseudoVLSE32_V_M8:
> - case RISCV::PseudoVLSE32_V_M8_MASK:
> - case RISCV::PseudoVLSE32_V_MF2:
> - case RISCV::PseudoVLSE32_V_MF2_MASK:
> - case RISCV::PseudoVSE32_V_M1:
> - case RISCV::PseudoVSE32_V_M1_MASK:
> - case RISCV::PseudoVSE32_V_M2:
> - case RISCV::PseudoVSE32_V_M2_MASK:
> - case RISCV::PseudoVSE32_V_M4:
> - case RISCV::PseudoVSE32_V_M4_MASK:
> - case RISCV::PseudoVSE32_V_M8:
> - case RISCV::PseudoVSE32_V_M8_MASK:
> - case RISCV::PseudoVSE32_V_MF2:
> - case RISCV::PseudoVSE32_V_MF2_MASK:
> - case RISCV::PseudoVSSE32_V_M1:
> - case RISCV::PseudoVSSE32_V_M1_MASK:
> - case RISCV::PseudoVSSE32_V_M2:
> - case RISCV::PseudoVSSE32_V_M2_MASK:
> - case RISCV::PseudoVSSE32_V_M4:
> - case RISCV::PseudoVSSE32_V_M4_MASK:
> - case RISCV::PseudoVSSE32_V_M8:
> - case RISCV::PseudoVSSE32_V_M8_MASK:
> - case RISCV::PseudoVSSE32_V_MF2:
> - case RISCV::PseudoVSSE32_V_MF2_MASK:
> + case RISCV::VLE32_V:
> + case RISCV::VLSE32_V:
> + case RISCV::VSE32_V:
> + case RISCV::VSSE32_V:
> return 32;
> - case RISCV::PseudoVLE64_V_M1:
> - case RISCV::PseudoVLE64_V_M1_MASK:
> - case RISCV::PseudoVLE64_V_M2:
> - case RISCV::PseudoVLE64_V_M2_MASK:
> - case RISCV::PseudoVLE64_V_M4:
> - case RISCV::PseudoVLE64_V_M4_MASK:
> - case RISCV::PseudoVLE64_V_M8:
> - case RISCV::PseudoVLE64_V_M8_MASK:
> - case RISCV::PseudoVLSE64_V_M1:
> - case RISCV::PseudoVLSE64_V_M1_MASK:
> - case RISCV::PseudoVLSE64_V_M2:
> - case RISCV::PseudoVLSE64_V_M2_MASK:
> - case RISCV::PseudoVLSE64_V_M4:
> - case RISCV::PseudoVLSE64_V_M4_MASK:
> - case RISCV::PseudoVLSE64_V_M8:
> - case RISCV::PseudoVLSE64_V_M8_MASK:
> - case RISCV::PseudoVSE64_V_M1:
> - case RISCV::PseudoVSE64_V_M1_MASK:
> - case RISCV::PseudoVSE64_V_M2:
> - case RISCV::PseudoVSE64_V_M2_MASK:
> - case RISCV::PseudoVSE64_V_M4:
> - case RISCV::PseudoVSE64_V_M4_MASK:
> - case RISCV::PseudoVSE64_V_M8:
> - case RISCV::PseudoVSE64_V_M8_MASK:
> - case RISCV::PseudoVSSE64_V_M1:
> - case RISCV::PseudoVSSE64_V_M1_MASK:
> - case RISCV::PseudoVSSE64_V_M2:
> - case RISCV::PseudoVSSE64_V_M2_MASK:
> - case RISCV::PseudoVSSE64_V_M4:
> - case RISCV::PseudoVSSE64_V_M4_MASK:
> - case RISCV::PseudoVSSE64_V_M8:
> - case RISCV::PseudoVSSE64_V_M8_MASK:
> + case RISCV::VLE64_V:
> + case RISCV::VLSE64_V:
> + case RISCV::VSE64_V:
> + case RISCV::VSSE64_V:
> return 64;
> }
> }
>
>
>
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