[PATCH] D136075: [AArch64]SME2 Multi-vector - Index/Single/Multi Array Vectors LONG INT MLA sources

[Caroline via Phabricator via llvm-commits]

CarolineConcatto added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp:5431-5437
+  case Match_InvalidMemoryIndexedRange4UImm2:
+    return Error(
+        Loc,
+        "vector select offset must be an immediate range of the form "
+        "<immf>:<imml>, "
+        "where the first immediate is a multiple of 4 in the range [0, 12] "
+        "and the second immediate is immf + 3.");
----------------
paulwalker-arm wrote:
> I cannot see any tests for this diagnostic.
Paul, I could not make the parser print this error message. It always end up being matched with 
class MCK_UImm1s4Range to print the error message. 

Maybe we can improve this, but I don't believe it should be in this patch. 
Probably I need to create another to fix this and probably 
 Match_InvalidMemoryIndexedRange2UImm2
Match_InvalidMemoryIndexedRange2UImm3
too.

The problems is with the parser 
Because I can see the instruction is being checked with the correct instruction.
Trying to match opcode SUMLALL_MZZI_BtoS for SUMLALL za.s[w8, 9:12], z22.b, z1.b[2]
  Matching formal operand class MCK_UImm2s4Range against actual operand at index 4 (<immrange 9:12>): Opcode result: multiple operand mismatches, ignoring this opcode
But for some reason it prints error for another instructions:
UMLALL_VG4_M4ZZI_BtoS
  Matching formal operand class MCK_UImm1s4Range against actual operand at index 4 (<immrange 9:12>): Opcode result: multiple operand mismatches, ignoring this opcode


================
Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:2101
+  bits<2> Rv;
+  bits<4> i;
+  bits<5> Zn;
----------------
paulwalker-arm wrote:
> `bits<3>`?
Oh...dear!


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D136075/new/

https://reviews.llvm.org/D136075