[PATCH] D136945: [AMDGPU] Enable `permlanex16` selection with `+16-bit-insts,+gfx10-insts`

[Pierre van Houtryve via Phabricator via llvm-commits]

Pierre-vh created this revision.
Pierre-vh added reviewers: arsenm, foad, Joe_Nash.
Herald added subscribers: kosarev, kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, jvesely, kzhuravl.
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ROCm device libs can emit permlanex w/ the +gfx10-insts attribute, and it counts on the optimizer to remove the call if the GPU is <GFX10.
When built at O0 it caused codegen issues as Clang allowed this intrinsic to go through with just +gfx10-insts, but the backend wanted the GPU to be >=GFX10 as well.

This patch allows selecting that intrinsic when just minimum required attributes are present. That is, +gfx10-insts & +16-bit-insts.

Depends on D136944 <https://reviews.llvm.org/D136944>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D136945

Files:
  llvm/lib/Target/AMDGPU/AMDGPU.td
  llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
  llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
  llvm/lib/Target/AMDGPU/GCNSubtarget.h
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/VOP3Instructions.td
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll

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