[llvm] 9bb1e21 - [AMDGPU] Clean up calls to MachineOperand::setIsDead and friends. NFC.
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 28 02:44:14 PDT 2022
Author: Jay Foad
Date: 2022-10-28T10:44:08+01:00
New Revision: 9bb1e21f07a21f0a2d8d9265bb8a7fbd986042c7
URL: https://github.com/llvm/llvm-project/commit/9bb1e21f07a21f0a2d8d9265bb8a7fbd986042c7
DIFF: https://github.com/llvm/llvm-project/commit/9bb1e21f07a21f0a2d8d9265bb8a7fbd986042c7.diff
LOG: [AMDGPU] Clean up calls to MachineOperand::setIsDead and friends. NFC.
Added:
Modified:
llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp b/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
index 95557cd2fbc5d..de245ef57def7 100644
--- a/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
@@ -711,7 +711,7 @@ bool GCNDPPCombine::combineDPPMov(MachineInstr &MovMI) const {
continue;
}
while (!S.second.empty())
- S.first->getOperand(S.second.pop_back_val()).setIsUndef(true);
+ S.first->getOperand(S.second.pop_back_val()).setIsUndef();
}
}
diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
index fb300e81cca8a..e760575cb586e 100644
--- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -1845,13 +1845,13 @@ bool GCNHazardRecognizer::fixShift64HighRegBug(MachineInstr *MI) {
Amt->setReg(NewAmt);
Amt->setIsKill(false);
// We do not update liveness, so verifier may see it as undef.
- Amt->setIsUndef(true);
+ Amt->setIsUndef();
if (OverlappedDst)
MI->getOperand(0).setReg(NewReg);
if (OverlappedSrc) {
Src1->setReg(NewReg);
Src1->setIsKill(false);
- Src1->setIsUndef(true);
+ Src1->setIsUndef();
}
return true;
diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
index f8b2c907799f6..fe5090f9c01c2 100644
--- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
@@ -328,7 +328,7 @@ void SIFrameLowering::emitEntryFunctionFlatScratchInit(
AMDGPU::FLAT_SCR_HI)
.addReg(FlatScrInitLo, RegState::Kill)
.addImm(8);
- LShr->getOperand(3).setIsDead(true); // Mark SCC as dead.
+ LShr->getOperand(3).setIsDead(); // Mark SCC as dead.
}
// Note SGPRSpill stack IDs should only be used for SGPR spilling to VGPRs, not
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 6e0478ed2f166..24ef9fdb7b8cf 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -4282,7 +4282,7 @@ MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter(
const DebugLoc &DL = MI.getDebugLoc();
MachineInstr *Br = BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_CBRANCH_SCC1))
.add(MI.getOperand(0));
- Br->getOperand(1).setIsUndef(true); // read undef SCC
+ Br->getOperand(1).setIsUndef(); // read undef SCC
MI.eraseFromParent();
return BB;
}
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 1a3c11cf1d014..f975b61f318c0 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -5588,7 +5588,7 @@ emitLoadSRsrcFromVGPRLoop(const SIInstrInfo &TII, MachineRegisterInfo &MRI,
// Update Rsrc operand to use the SGPR Rsrc.
Rsrc.setReg(SRsrc);
- Rsrc.setIsKill(true);
+ Rsrc.setIsKill();
Register SaveExec = MRI.createVirtualRegister(BoolXExecRC);
MRI.setSimpleHint(SaveExec, CondReg);
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 161eb5ecd458c..99292129257f2 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -228,7 +228,7 @@ struct SGPRSpillBuilder {
auto I = BuildMI(*MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg);
if (!TmpVGPRLive)
I.addReg(TmpVGPR, RegState::ImplicitDefine);
- I->getOperand(2).setIsDead(true); // Mark SCC as dead.
+ I->getOperand(2).setIsDead(); // Mark SCC as dead.
TRI.buildVGPRSpillLoadStore(*this, TmpVGPRIndex, 0, /*IsLoad*/ false);
}
}
@@ -263,7 +263,7 @@ struct SGPRSpillBuilder {
auto I = BuildMI(*MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg);
if (!TmpVGPRLive)
I.addReg(TmpVGPR, RegState::ImplicitKill);
- I->getOperand(2).setIsDead(true); // Mark SCC as dead.
+ I->getOperand(2).setIsDead(); // Mark SCC as dead.
// Restore active lanes
if (TmpVGPRLive)
@@ -2197,7 +2197,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
Register TmpReg = RS->scavengeRegister(RC, MI, 0, !UseSGPR);
FIOp.setReg(TmpReg);
- FIOp.setIsKill(true);
+ FIOp.setIsKill();
if ((!FrameReg || !Offset) && TmpReg) {
unsigned Opc = UseSGPR ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
@@ -2270,8 +2270,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
.addImm(ST.getWavefrontSizeLog2())
.addReg(FrameReg);
if (IsSALU && !LiveSCC)
- Shift.getInstr()->getOperand(3).setIsDead(
- true); // Mark SCC as dead.
+ Shift.getInstr()->getOperand(3).setIsDead(); // Mark SCC as dead.
if (IsSALU && LiveSCC) {
Register NewDest =
RS->scavengeRegister(&AMDGPU::SReg_32RegClass, Shift, 0);
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