[PATCH] D136759: [AArch64][SVE2] Add the SVE2.1 while & pext predicate pair instructions

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64RegisterInfo.td:1000
+class PPRVectorListMul<int ElementWidth, int NumRegs> : PPRVectorList<ElementWidth, NumRegs> {
+  let Name = "SMEPredicateListMul" # NumRegs # "x" # ElementWidth;
+  let DiagnosticType = "Invalid" # Name;
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`SVEPredicateListMul`


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Comment at: llvm/lib/Target/AArch64/AArch64RegisterInfo.td:1009
+    DecoderMethod = "DecodePPR2Mul2RegisterClass" in {
+  def PP_b_mul : RegisterOperand<PPR2Mul2, "printTypedVectorList<0,'b'>"> {
+    let ParserMatchClass = PPRVectorListMul<8, 2>;
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Should this be `PP_b_mul_r` to match the style used by `ZZ_b_mul_r`?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136759/new/

https://reviews.llvm.org/D136759