[PATCH] D136750: [AArch64][SVE2] Add the SVE2.1 while predicate-as-counter instructions
Paul Walker via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 27 17:04:05 PDT 2022
paulwalker-arm added inline comments.
================
Comment at: llvm/test/MC/AArch64/SVE2p1/whilege-diagnostics.s:6
+
+whilege pn8.b, x0, x0, vlx1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
----------------
I think it's worth testing `whilege pn8.b, x0, x0`. Hopefully we get a nice error like "... expected vl specifier".
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D136750/new/
https://reviews.llvm.org/D136750
More information about the llvm-commits
mailing list