[PATCH] D136750: [AArch64][SVE2] Add the SVE2.1 while predicate-as-counter instructions

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


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Comment at: llvm/test/MC/AArch64/SVE2p1/whilege-diagnostics.s:6
+
+whilege pn8.b, x0, x0, vlx1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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I think it's worth testing `whilege pn8.b, x0, x0`. Hopefully we get a nice error like "... expected vl specifier".


Repository:
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  https://reviews.llvm.org/D136750/new/

https://reviews.llvm.org/D136750