[PATCH] D136880: [test] Remove readonly from some parameters that are written through in tests.

Patrick Walton via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Oct 27 13:08:06 PDT 2022 

pcwalton created this revision.
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In D136659 <https://reviews.llvm.org/D136659> I found a few tests that write through readonly parameters:

- Analysis/BasicAA/pr18573.ll: @foo1 writes through %arr.ptr, but declares it

readonly. I removed the readonly annotation.

- CodeGen/ARM/ParallelDSP/aliasing.ll: @restrict writes through the readonly

%arg3, @store_alias_arg3_illegal_1 writes through the readonly %arg3, and
@store_alias_arg3_illegal_2 writes through the readonly %arg3. I removed
readonly from all three. Also, I added some CHECK-LABEL directives to make it
harder for FileCheck output to be mixed up.

- Transforms/LoopVectorize/AArch64/sve-gather-scatter.ll:

@gather_nxv4i32_ind64_stride2 writes through the readonly %a. I removed the
readonly attribute.

- Transforms/LoopVectorize/interleaved-accesses.ll: @load_gap_reverse writes

through the readonly %P1 <https://reviews.llvm.org/P1> and %P2 <https://reviews.llvm.org/P2>. Also, the corresponding C code in the comment
didn't match the test. I removed the readonly attribute from both parameters
and corrected the C code.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D136880

Files:
  llvm/test/Analysis/BasicAA/pr18573.ll
  llvm/test/CodeGen/ARM/ParallelDSP/aliasing.ll
  llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter.ll
  llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll


Index: llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
===================================================================
--- llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
+++ llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
@@ -572,15 +572,15 @@
 ; void load_gap_reverse(struct pair *P1, struct pair *P2, int X) {
 ;   for (int i = 1023; i >= 0; i--) {
 ;     int a = X + i;
-;     int b = A[i].y - i;
-;     B[i].x = a;
+;     int b = B[i].y - i;
+;     A[i].x = a;
 ;     B[i].y = b;
 ;   }
 ; }
 
 
 %pair = type { i64, i64 }
-define void @load_gap_reverse(%pair* noalias nocapture readonly %P1, %pair* noalias nocapture readonly %P2, i64 %X) {
+define void @load_gap_reverse(%pair* noalias nocapture %P1, %pair* noalias nocapture %P2, i64 %X) {
 ; CHECK-LABEL: @load_gap_reverse(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
Index: llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter.ll
===================================================================
--- llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter.ll
+++ llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter.ll
@@ -292,7 +292,7 @@
 
 
 
-define void @gather_nxv4i32_ind64_stride2(float* noalias nocapture readonly %a, float* noalias nocapture readonly %b, i64 %n) #0 {
+define void @gather_nxv4i32_ind64_stride2(float* noalias nocapture %a, float* noalias nocapture readonly %b, i64 %n) #0 {
 ; CHECK-LABEL: @gather_nxv4i32_ind64_stride2(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
Index: llvm/test/CodeGen/ARM/ParallelDSP/aliasing.ll
===================================================================
--- llvm/test/CodeGen/ARM/ParallelDSP/aliasing.ll
+++ llvm/test/CodeGen/ARM/ParallelDSP/aliasing.ll
@@ -4,6 +4,7 @@
 ; instruction possibly aliasing any mul load operands; arguments are passed
 ; without 'restrict' enabled.
 ;
+; CHECK-LABEL: @no_restrict
 ; CHECK-NOT:  call i32 @llvm.arm.smlad
 ;
 define dso_local i32 @no_restrict(i32 %arg, i32* nocapture %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
@@ -52,9 +53,10 @@
 ; aliasing one of the mul load operands. Arguments are now annotated with
 ; 'noalias'.
 ;
+; CHECK-LABEL: @restrict
 ; CHECK-NOT:  call i32 @llvm.arm.smlad
 ;
-define dso_local i32 @restrict(i32 %arg, i32* noalias %arg1, i16* noalias readonly %arg2, i16* noalias readonly %arg3) {
+define dso_local i32 @restrict(i32 %arg, i32* noalias %arg1, i16* noalias readonly %arg2, i16* noalias %arg3) {
 entry:
   %cmp24 = icmp sgt i32 %arg, 0
   br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
@@ -289,7 +291,7 @@
 
 ; CHECK-LABEL: store_alias_arg3_illegal_1
 ; CHECK-NOT: load i32
-define dso_local i32 @store_alias_arg3_illegal_1(i32 %arg, i32* nocapture %arg1, i16* noalias nocapture readonly %arg2, i16* noalias nocapture readonly %arg3) {
+define dso_local i32 @store_alias_arg3_illegal_1(i32 %arg, i32* nocapture %arg1, i16* noalias nocapture readonly %arg2, i16* noalias nocapture %arg3) {
 entry:
   %cmp24 = icmp sgt i32 %arg, 0
   br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
@@ -330,7 +332,7 @@
 
 ; CHECK-LABEL: store_alias_arg3_illegal_2
 ; CHECK-NOT: load i32
-define dso_local i32 @store_alias_arg3_illegal_2(i32 %arg, i32* nocapture %arg1, i16* noalias nocapture readonly %arg2, i16* noalias nocapture readonly %arg3) {
+define dso_local i32 @store_alias_arg3_illegal_2(i32 %arg, i32* nocapture %arg1, i16* noalias nocapture readonly %arg2, i16* noalias nocapture %arg3) {
 entry:
   %cmp24 = icmp sgt i32 %arg, 0
   br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
@@ -455,7 +457,7 @@
 ; when it finds the alias.
 ; CHECK-LABEL: one_pair_alias
 ; CHECK-NOT: call i32 @llvm.arm.smlad
-define i32 @one_pair_alias(i16* noalias nocapture readonly %b, i16* noalias nocapture readonly %c) {
+define i32 @one_pair_alias(i16* noalias nocapture readonly %b, i16* noalias nocapture %c) {
 entry:
   br label %for.body
 
Index: llvm/test/Analysis/BasicAA/pr18573.ll
===================================================================
--- llvm/test/Analysis/BasicAA/pr18573.ll
+++ llvm/test/Analysis/BasicAA/pr18573.ll
@@ -8,7 +8,7 @@
 declare <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float>, i8*, <8 x i32>, <8 x float>, i8) #0
 
 ; Function Attrs: nounwind
-define <8 x float> @foo1(i8* noalias readonly %arr.ptr, <8 x i32>* noalias readonly %vix.ptr, i8* noalias %t2.ptr) #1 {
+define <8 x float> @foo1(i8* noalias %arr.ptr, <8 x i32>* noalias readonly %vix.ptr, i8* noalias %t2.ptr) #1 {
 allocas:
   %vix = load <8 x i32>, <8 x i32>* %vix.ptr, align 4
   %t1.ptr = getelementptr i8, i8* %arr.ptr, i8 4


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