[PATCH] D136091: [AArch64] SME2 multi-vec unpack and ZIP two and four registers

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64RegisterInfo.td:1116
+
+  def ZZ_q_mul_r : RegisterOperand<ZPR2, "printTypedVectorList<0,'q'>"> {
+    let ParserMatchClass = ZPRVectorListMul<128, 2>;
----------------
I'd expect this to be `ZPR2Mul2`?


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Comment at: llvm/lib/Target/AArch64/AArch64RegisterInfo.td:1139
+
+  def ZZZZ_q_mul_r : RegisterOperand<ZPR4, "printTypedVectorList<0,'q'>"> {
+    let ParserMatchClass = ZPRVectorListMul<128, 4>;
----------------
`ZPR4Mul4`?


================
Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:1820
 
-class sme2_fp_cvt_vg4_multi<string mnemonic, bits<3> op>
-    : I<(outs ZZZZ_s_mul_r:$Zd), (ins ZZZZ_s_mul_r:$Zn),
+class sme2_zip_cvt_vg4_multi<bits<2> sz, bits<2> op1, bits<3> op2,
+                             bit op3, RegisterOperand first_vector_ty,
----------------
Have you reached the point where this class can just represent `SME2 Multi-vector - SVE Constructive Unary`?  Perhaps not all instructions within that encoding group fit but looking at this new definition of `Inst`, which I very much like by the way, suggests that is what this class effectively represents. So you just need to change a few opcodes to match the documentation.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136091/new/

https://reviews.llvm.org/D136091