[llvm] 8fa32a7 - [RISCV] Fix an obvious CSE opportunity in LSR test case. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-10-27T10:36:44-07:00
New Revision: 8fa32a74cf1ddb44812505f30f2d970cd507adbb

URL: https://github.com/llvm/llvm-project/commit/8fa32a74cf1ddb44812505f30f2d970cd507adbb
DIFF: https://github.com/llvm/llvm-project/commit/8fa32a74cf1ddb44812505f30f2d970cd507adbb.diff

LOG: [RISCV] Fix an obvious CSE opportunity in LSR test case. NFC

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/loop-strength-reduce-add-cheaper-than-mul.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/loop-strength-reduce-add-cheaper-than-mul.ll b/llvm/test/CodeGen/RISCV/loop-strength-reduce-add-cheaper-than-mul.ll
index 25d32d76dbce..4f11dcb51b7f 100644
--- a/llvm/test/CodeGen/RISCV/loop-strength-reduce-add-cheaper-than-mul.ll
+++ b/llvm/test/CodeGen/RISCV/loop-strength-reduce-add-cheaper-than-mul.ll
@@ -75,13 +75,12 @@ define void @test(i32 signext %i) nounwind {
 entry:
 	%k_addr.012 = shl i32 %i, 1
 	%tmp14 = icmp sgt i32 %k_addr.012, 8192
-	%tmp. = shl i32 %i, 1
 	br i1 %tmp14, label %return, label %bb
 
 bb:
 	%indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ]
 	%tmp.15 = mul i32 %indvar, %i
-	%tmp.16 = add i32 %tmp.15, %tmp.
+	%tmp.16 = add i32 %tmp.15, %k_addr.012
 	%gep.upgrd.1 = zext i32 %tmp.16 to i64
 	%tmp = getelementptr [8193 x i8], [8193 x i8]* @flags2, i32 0, i64 %gep.upgrd.1
 	store i8 0, i8* %tmp