[PATCH] D136663: Handling ADD|SUB U64 decomposed Pseudos not getting lowered to SDWA form

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp:873
+  if (!TII->canShrink(MISucc, *MRI) &&
+      !TII->getNamedOperand(MI, AMDGPU::OpName::src1)->isReg())
     return;
----------------
arsenm wrote:
> yassingh wrote:
> > rampitec wrote:
> > > yassingh wrote:
> > > > rampitec wrote:
> > > > > This can be inline literal and still useful I suppose.
> > > > Sorry I don't understand, are you suggesting moving this condition to a string literal?
> > > I mean bailing on non-register operand limits the pass. The src1 operand can be inline literal and still convertible to sdwa form.
> > Earlier we were checking if the instruction is not shrinkable don't proceed. Now we are also checking whether the reason for not shrinking is src1 being an immediate operand. 
> > Hence we are covering src1 being an inline literal(correct me if I'm wrongly assuming that inline literal means immediate operand)
> Inline immediate ares the ones that are free to encode in vsrc0, or in all vsrc operands for VOP3, as opposed to other literals that require materialization in a register. See TII::isInlineConstant 
If an immediate is an inline literal instruction is still shrinkable. For example if it is 0 or 1 it is shrinkable, if it is 100 it is not.


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  https://reviews.llvm.org/D136663/new/

https://reviews.llvm.org/D136663