[PATCH] D134949: [AMDGPU] Use the right frame register in custom CSR spills

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIFrameLowering.cpp:1082-1083
+
+  if (TRI.hasStackRealignment(MF))
     HasFP = true;
+
----------------
Don't understand why this is special cased when you also call hasFP below


================
Comment at: llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h:368
   };
+  bool Ignore = false;
 
----------------
arsenm wrote:
> I don't understand what this is supposed to mean
I still don’t understand what ignored really man’s or why it would occur


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134949/new/

https://reviews.llvm.org/D134949