[PATCH] D136847: [RISCV][NFC] Mark rs1 in most memory instructions as memory operand.

[Dmitry via Phabricator via llvm-commits]

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Marking rs1 (memory offset base) as memory operand provides additional
semantic value to this operand that can be used by different tools
(e.g. llvm-exegesis).

This change does not affect neigther Isel nor assembler. However it
required some tweaks in tablegen compressed inst emmiter.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D136847

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoC.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/utils/TableGen/CompressInstEmitter.cpp

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