[PATCH] D136678: [AArch64][SVE2] Add the SVE2.1 pext and ptrue predicate-as-counter instructions

[David Sherwood via Phabricator via llvm-commits]

david-arm marked 2 inline comments as done.
david-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp:1203
 
+  template <unsigned Class> bool isSMEVectorReg() const {
+    RegKind RK;
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paulwalker-arm wrote:
> `isSVEPredicateReg()`?
There is already a `isSVEPredicateReg`, so I've renamed this to `isSVEPredicateAsCounterReg`.


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Comment at: llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp:2598-2605
+      .Case("pn0", AArch64::P0)
+      .Case("pn1", AArch64::P1)
+      .Case("pn2", AArch64::P2)
+      .Case("pn3", AArch64::P3)
+      .Case("pn4", AArch64::P4)
+      .Case("pn5", AArch64::P5)
+      .Case("pn6", AArch64::P6)
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paulwalker-arm wrote:
> Can these ever be hit? or does it help with diagnostics or something?
Yes this is hit even in the positive path due to this call chain:

  tryParseVectorRegister -> matchRegisterNameAlias -> matchSVEPredicateAsCounterRegName


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136678/new/

https://reviews.llvm.org/D136678