[PATCH] D136814: [RISCV][NFC] Remove ISel of SPLAT_VECTOR

[Wang Pengcheng via Phabricator via llvm-commits]

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Since we have converted SPLAT_VECTOR to VMV_V_X_VL
or VFMV_V_F_VL in RISCVDAGToDAGISel::PreprocessISelDAG().


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D136814

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp


Index: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -1786,7 +1786,6 @@
     ReplaceNode(Node, Extract.getNode());
     return;
   }
-  case ISD::SPLAT_VECTOR:
   case RISCVISD::VMV_S_X_VL:
   case RISCVISD::VFMV_S_F_VL:
   case RISCVISD::VMV_V_X_VL:
@@ -1794,10 +1793,9 @@
     // Try to match splat of a scalar load to a strided load with stride of x0.
     bool IsScalarMove = Node->getOpcode() == RISCVISD::VMV_S_X_VL ||
                         Node->getOpcode() == RISCVISD::VFMV_S_F_VL;
-    bool HasPassthruOperand = Node->getOpcode() != ISD::SPLAT_VECTOR;
-    if (HasPassthruOperand && !Node->getOperand(0).isUndef())
+    if (!Node->getOperand(0).isUndef())
       break;
-    SDValue Src = HasPassthruOperand ? Node->getOperand(1) : Node->getOperand(0);
+    SDValue Src = Node->getOperand(1);
     auto *Ld = dyn_cast<LoadSDNode>(Src);
     if (!Ld)
       break;
@@ -1810,9 +1808,7 @@
       break;
 
     SDValue VL;
-    if (Node->getOpcode() == ISD::SPLAT_VECTOR)
-      VL = CurDAG->getTargetConstant(RISCV::VLMaxSentinel, DL, XLenVT);
-    else if (IsScalarMove) {
+    if (IsScalarMove) {
       // We could deal with more VL if we update the VSETVLI insert pass to
       // avoid introducing more VSETVLI.
       if (!isOneConstant(Node->getOperand(2)))


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