[PATCH] D136788: [InstCombine] improve demanded bits for Sub operand 0

[Sanjay Patel via Phabricator via llvm-commits]

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This is copying the code that was added for `add` with D130075 <https://reviews.llvm.org/D130075>. (That patch removed a fallthrough in the cases, but we can probably still share at least some code again as a follow-up cleanup, but I didn't want to risk it here.)

The reasoning is similar to the carry propagation for `add`: if we don't demand low bits of the subtraction and the subtrahend (aka RHS or operand 1) is known zero in those low bits, then there can't be any borrowing required from the higher bits of operand 0, so they don't matter.

Also, the no-wrap flags can be propagated (and I think that should be true for `add` too).

Here's an attempt to prove that in Alive2:
https://alive2.llvm.org/ce/z/xqh7Pa
(can add nsw or nuw from `src` and `tgt`, and it should still pass)


https://reviews.llvm.org/D136788

Files:
  llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
  llvm/test/Transforms/InstCombine/sub.ll

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