[PATCH] D136158: [AArch64] Adjust operand sequence for Add+Sub to combine more inline shift

[Dave Green via Phabricator via llvm-commits]

dmgreen accepted this revision.
dmgreen added a comment.
This revision is now accepted and ready to land.

Thanks for finding the problem. This LGTM now.

> Or can we do it on Machine IR(AArch64MIPeepholeOpt) to avoid dead loop and also GISel can get benefit?

I was wondering what to do about optimizations that can be shared between GISel and SDAG. AArch64MIPeepholeOpt often feels like the wrong place (MachineCombiner might be better for some optimizations like this one, but that currently doesn't scale very well). We don't really want to write them in the wrong place if they would be better as combines during ISel. For now at least this patch looks good.


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