[PATCH] D136678: [AArch64][SVE2] Add the SVE2.1 pext and ptrue predicate-as-counter instructions

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64RegisterInfo.td:883
+def PPR_3b : PPRClass<0, 7>; // Restricted 3 bit SVE predicate register class.
+def PPR_3b_p8_p15 : PPRClass<8, 15>;
 
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paulwalker-arm wrote:
> Given you specify the range does the `_3b` part provide any value? I'd rather just `PPR_p8_p15` or even `PPR_p8to15`.
It would be nice to also rename `PPR_3b` to `PPR_p0to7` in that case (although preferably not as part of this patch)


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Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:3590
+
+defm PEXT_PCI : sve2p1_int_ctr_to_mask<"pext">;
+defm PTRUE_C  : sve2p1_ptrue_pn<"ptrue">;
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nit: what does the `int` here mean?


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Comment at: llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp:3889-3913
+
+  // But when they do they shouldn't have an element type suffix.
+  if (!Kind.empty()) {
+    Error(S, "not expecting size suffix");
+    return MatchOperand_ParseFail;
+  }
+
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This code is currently untested by this patch.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136678/new/

https://reviews.llvm.org/D136678