[PATCH] D136738: [RISCV] Optimize i64 insertelt on RV32.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
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We can use tail undisturbed vslide1down to insert into the vector.

This should make D136640 <https://reviews.llvm.org/D136640> unneeded.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D136738

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll

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