[PATCH] D136713: [SDAG] avoid vector extract/insert around binop

[Sanjay Patel via Phabricator via llvm-commits]

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scalar-to-vector (binop (extractelt V, Idx), C) --> shuffle (bo V, C'), {Idx, -1, -1...}

We generally try to avoid ad-hoc vectorization in SDAG, but the motivating case from issue #39482 <https://github.com/llvm/llvm-project/issues/39482>
escapes our normal vectorization folds in IR. It seems like it should always be a win to transform this pattern in cases where we have the same vector type for input and output and the target supports the vector operation because we avoid transfers from vector to scalar and back.

In the x86 shift examples, we create the scalar-to-vector node during legalization. I'm not sure if there's a more general way to create the pattern for testing. (If so, I could add tests for other targets.)


https://reviews.llvm.org/D136713

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/X86/cvt16.ll
  llvm/test/CodeGen/X86/half.ll
  llvm/test/CodeGen/X86/urem-vector-lkk.ll
  llvm/test/CodeGen/X86/vec_shift5.ll

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