[llvm] fcbaf6f - [X86] Add v4i64 test coverage for #58585
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 25 07:03:23 PDT 2022
Author: Simon Pilgrim
Date: 2022-10-25T15:03:08+01:00
New Revision: fcbaf6f4e8bd1d39c5f0bcffab4bc26173b46877
URL: https://github.com/llvm/llvm-project/commit/fcbaf6f4e8bd1d39c5f0bcffab4bc26173b46877
DIFF: https://github.com/llvm/llvm-project/commit/fcbaf6f4e8bd1d39c5f0bcffab4bc26173b46877.diff
LOG: [X86] Add v4i64 test coverage for #58585
Turns out we fail to do this for concat_v4i64(broadcast_v2i64,broadcast_v2i64) as well
Added:
Modified:
llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll b/llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll
index ab972feef285..5f5b799a4c6c 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll
@@ -1540,6 +1540,33 @@ define <4 x i64> @shuffle_v4i64_1z3z(<4 x i64> %a, <4 x i64> %b) {
ret <4 x i64> %shuffle
}
+define <4 x i64> @shuffle_v4i64_0044_v2i64(<2 x i64> %a, <2 x i64> %b) {
+; AVX1-LABEL: shuffle_v4i64_0044_v2i64:
+; AVX1: # %bb.0:
+; AVX1-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
+; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: shuffle_v4i64_0044_v2i64:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
+; AVX2-NEXT: vmovddup {{.*#+}} xmm1 = xmm1[0,0]
+; AVX2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT: retq
+;
+; AVX512VL-LABEL: shuffle_v4i64_0044_v2i64:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
+; AVX512VL-NEXT: vmovddup {{.*#+}} xmm1 = xmm1[0,0]
+; AVX512VL-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX512VL-NEXT: retq
+ %1 = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
+ %2 = shufflevector <2 x i64> %b, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
+ %3 = shufflevector <2 x i64> %1, <2 x i64> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ ret <4 x i64> %3
+}
+
define <4 x i64> @shuffle_v4i64_1032_v2i64(<2 x i64> %a, <2 x i64> %b) {
; ALL-LABEL: shuffle_v4i64_1032_v2i64:
; ALL: # %bb.0:
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