[PATCH] D136525: [M68k] Add codegen pattern for atomic load / store

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

In D136525#3882193 <https://reviews.llvm.org/D136525#3882193>, @0x59616e wrote:

> In D136525#3880337 <https://reviews.llvm.org/D136525#3880337>, @efriedma wrote:
>
>> Are multi-processor m68k computers a thing?  I can't find any reference to such a thing existing, but the manual indicates that the processor was designed to allow it.  If it does exist, m68k probably needs to use sequences similar to x86.  (x86 didn't have any barrier instruction for a long time, but a "lock" instruction has the right semantics.)
>
> **Take my word with a pinch of salt**
>
> We may have to use the compare-and-swap instruction to reach that (or with the aid of glibc). But is it necessary on such an old architecture that may not have all the modern technologies such as out-of-order execution and store/write buffer --- which are the reasons the atomic instruction or memory barrier exists for ?

I can't remember any details (so long ago, sniff) - but wasn't TAS (test and set) used as an alternative to CAS which only appeared on 68020 and later? I vaguely remember on Amigas, which although not truly multi-processor had a lot of custom chips accessing some of the memory at the same time, you had to be very careful about using TAS/CAS.


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