[PATCH] D136675: [MachineCSE] Allow PRE of instructions that read physical registers

[John Brawn via Phabricator via llvm-commits]

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Currently MachineCSE forbids PRE when the instruction reads a physical register. Relax this so that it's allowed when the value being read is the same as what would be read in the place the instruction would be hoisted to.

This is being done in preparation for adding FPCR handling to the AArch64 backend, in order to prevent it to from worsening the generated code, but for targets that already have a similar register it should improve things.

This patch affects code generation in several tests. The new code looks better except for in Thumb2/LowOverheadLoops/memcall.ll where we perform PRE but the LowOverheadLoops transformation then undoes it. Also in AMDGPU/selectcc-opt.ll the CHECK makes things look worse, but actually the function as a whole is better (as a MOV is PRE'd).


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D136675

Files:
  llvm/lib/CodeGen/MachineCSE.cpp
  llvm/test/CodeGen/AMDGPU/GlobalISel/hip.extern.shared.array.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
  llvm/test/CodeGen/AMDGPU/selectcc-opt.ll
  llvm/test/CodeGen/PowerPC/machine-cse-rm-pre.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/memcall.ll

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