[PATCH] D136244: [AArch64] Optimize memcmp when the result is tested for [in]equality with 0

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:19509-19510
+    SDValue Overflow = Cmp.getValue(1);
+    // Clear the Z bit. (As the EQ is a && and the NE is a ||, it might be
+    // simpler to just use a constant of 0 in both cases)
+    SDValue NZCVOp = DAG.getConstant(AArch64CC::EQ, DL, MVT::i32);
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This comment doesn't seem very helpful as a code-comment.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:19511
+    // simpler to just use a constant of 0 in both cases)
+    SDValue NZCVOp = DAG.getConstant(AArch64CC::EQ, DL, MVT::i32);
+    SDValue CCmp = DAG.getNode(AArch64ISD::CCMP, DL, MVT_CC, XOR1.getOperand(0),
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AArch64CC::EQ -> 0 is probably better. It is not a condition, but the value the NZCV flags are set to.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:19503
+    SDValue XOR1 = LHS.getOperand(1);
+    SDValue CCVal = DAG.getConstant(0, DL, MVT_CC);
+    EVT TstVT = LHS->getValueType(0);
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0 -> AArch64CC::EQ.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:19506
+    SDValue Cmp =
+        DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(TstVT, MVT::Glue),
+                    XOR0.getOperand(0), XOR0.getOperand(1));
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I'm not sure if this should be MVT::Glue or MVT::i32. It seems to be created differently in different places.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136244/new/

https://reviews.llvm.org/D136244