[llvm] ecd78ec - [AArch64]SME2 Multiple vectors Int/FP clamp instructions for two/four registers
Caroline Concatto via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 25 01:12:47 PDT 2022
Author: Caroline Concatto
Date: 2022-10-25T09:12:27+01:00
New Revision: ecd78ec5b98ca77010c1c22eed64699e5e4c7a8e
URL: https://github.com/llvm/llvm-project/commit/ecd78ec5b98ca77010c1c22eed64699e5e4c7a8e
DIFF: https://github.com/llvm/llvm-project/commit/ecd78ec5b98ca77010c1c22eed64699e5e4c7a8e.diff
LOG: [AArch64]SME2 Multiple vectors Int/FP clamp instructions for two/four registers
This patch adds the assembly/disassembly for the following instruction:
Int:
SCLAMP:Multi-vector signed clamp to minimum/maximum vector.
UCLAMP:Multi-vector unsigned clamp to minimum/maximum vector.
FP:
FCLAMP: Multi-vector floating-point clamp to minimum/maximum number.
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09
Depends on: D135563
Differential Revision: https://reviews.llvm.org/D135601
Added:
llvm/test/MC/AArch64/SME2/fclamp-diagnostics.s
llvm/test/MC/AArch64/SME2/fclamp.s
llvm/test/MC/AArch64/SME2/sclamp-diagnostics.s
llvm/test/MC/AArch64/SME2/sclamp.s
llvm/test/MC/AArch64/SME2/uclamp-diagnostics.s
llvm/test/MC/AArch64/SME2/uclamp.s
Modified:
llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
llvm/lib/Target/AArch64/SMEInstrFormats.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
index 288915b784265..5234012e78d4b 100644
--- a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
@@ -420,6 +420,16 @@ defm URSHL_VG4_4ZZ : sme2_int_sve_destructive_vector_vg4_single<"urshl", 0b010
defm URSHL_VG2_2Z2Z : sme2_int_sve_destructive_vector_vg2_multi<"urshl", 0b0100011>;
defm URSHL_VG4_4Z4Z : sme2_int_sve_destructive_vector_vg4_multi<"urshl", 0b0100011>;
+defm FCLAMP_VG2_2Z2Z : sme2_fp_clamp_vector_vg2_multi<"fclamp">;
+defm FCLAMP_VG4_4Z4Z : sme2_fp_clamp_vector_vg4_multi<"fclamp">;
+
+defm SCLAMP_VG2_2Z2Z : sme2_int_clamp_vector_vg2_multi<"sclamp", 0b0>;
+defm SCLAMP_VG4_4Z4Z : sme2_int_clamp_vector_vg4_multi<"sclamp", 0b0>;
+
+defm UCLAMP_VG2_2Z2Z : sme2_int_clamp_vector_vg2_multi<"uclamp", 0b1>;
+defm UCLAMP_VG4_4Z4Z : sme2_int_clamp_vector_vg4_multi<"uclamp", 0b1>;
+
+
}
diff --git a/llvm/lib/Target/AArch64/SMEInstrFormats.td b/llvm/lib/Target/AArch64/SMEInstrFormats.td
index 0f4d3d52055db..29450032c86de 100644
--- a/llvm/lib/Target/AArch64/SMEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SMEInstrFormats.td
@@ -1860,3 +1860,72 @@ class sme2_fp_cvt_vg4_multi<string mnemonic, bits<3> op>
let Inst{4-2} = Zd;
let Inst{1-0} = 0b00;
}
+
+//===----------------------------------------------------------------------===//
+// SME2 multi-vec CLAMP registers
+
+class sme2_clamp_vector_vg24_multi<bits<2> sz, bits<2> op1, bit u,
+ RegisterOperand multi_vector_ty,
+ ZPRRegOp vector_ty, string mnemonic>
+ : I<(outs multi_vector_ty:$Zd),
+ (ins multi_vector_ty:$_Zd, vector_ty:$Zn, vector_ty:$Zm),
+ mnemonic, "\t$Zd, $Zn, $Zm",
+ "", []>, Sched<[]>{
+ bits<5> Zm;
+ bits<5> Zn;
+ let Inst{31-24} = 0b11000001;
+ let Inst{23-22} = sz;
+ let Inst{21} = 0b1;
+ let Inst{20-16} = Zm;
+ let Inst{15-12} = 0b1100;
+ let Inst{11-10} = op1;
+ let Inst{9-5} = Zn;
+ let Inst{0} = u;
+
+ let Constraints = "$Zd = $_Zd";
+}
+
+class sme2_clamp_vector_vg2_multi<bits<2> sz, bits<2> op1, bit u,
+ RegisterOperand multi_vector_ty,
+ ZPRRegOp vector_ty, string mnemonic>
+ : sme2_clamp_vector_vg24_multi<sz, op1, u, multi_vector_ty, vector_ty,
+ mnemonic>{
+ bits<4> Zd;
+ let Inst{4-1} = Zd;
+}
+
+multiclass sme2_fp_clamp_vector_vg2_multi<string mnemonic>{
+ def _H : sme2_clamp_vector_vg2_multi<0b01, 0b00, 0b0, ZZ_h_mul_r, ZPR16, mnemonic>;
+ def _S : sme2_clamp_vector_vg2_multi<0b10, 0b00, 0b0, ZZ_s_mul_r, ZPR32, mnemonic>;
+ def _D : sme2_clamp_vector_vg2_multi<0b11, 0b00, 0b0, ZZ_d_mul_r, ZPR64, mnemonic>;
+}
+
+multiclass sme2_int_clamp_vector_vg2_multi<string mnemonic, bit u>{
+ def _B : sme2_clamp_vector_vg2_multi<0b00, 0b01, u, ZZ_b_mul_r, ZPR8, mnemonic>;
+ def _H : sme2_clamp_vector_vg2_multi<0b01, 0b01, u, ZZ_h_mul_r, ZPR16, mnemonic>;
+ def _S : sme2_clamp_vector_vg2_multi<0b10, 0b01, u, ZZ_s_mul_r, ZPR32, mnemonic>;
+ def _D : sme2_clamp_vector_vg2_multi<0b11, 0b01, u, ZZ_d_mul_r, ZPR64, mnemonic>;
+}
+
+class sme2_clamp_vector_vg4_multi<bits<2> sz, bits<2> op1, bit u,
+ RegisterOperand multi_vector_ty,
+ ZPRRegOp vector_ty, string mnemonic>
+ : sme2_clamp_vector_vg24_multi<sz, op1, u, multi_vector_ty, vector_ty,
+ mnemonic>{
+ bits<3> Zd;
+ let Inst{4-2} = Zd;
+ let Inst{1} = 0b0;
+}
+
+multiclass sme2_fp_clamp_vector_vg4_multi<string mnemonic>{
+ def _H : sme2_clamp_vector_vg4_multi<0b01, 0b10, 0b0, ZZZZ_h_mul_r, ZPR16, mnemonic>;
+ def _S : sme2_clamp_vector_vg4_multi<0b10, 0b10, 0b0, ZZZZ_s_mul_r, ZPR32, mnemonic>;
+ def _D : sme2_clamp_vector_vg4_multi<0b11, 0b10, 0b0, ZZZZ_d_mul_r, ZPR64, mnemonic>;
+}
+
+multiclass sme2_int_clamp_vector_vg4_multi<string mnemonic, bit u>{
+ def _B : sme2_clamp_vector_vg4_multi<0b00, 0b11, u, ZZZZ_b_mul_r, ZPR8, mnemonic>;
+ def _H : sme2_clamp_vector_vg4_multi<0b01, 0b11, u, ZZZZ_h_mul_r, ZPR16, mnemonic>;
+ def _S : sme2_clamp_vector_vg4_multi<0b10, 0b11, u, ZZZZ_s_mul_r, ZPR32, mnemonic>;
+ def _D : sme2_clamp_vector_vg4_multi<0b11, 0b11, u, ZZZZ_d_mul_r, ZPR64, mnemonic>;
+}
diff --git a/llvm/test/MC/AArch64/SME2/fclamp-diagnostics.s b/llvm/test/MC/AArch64/SME2/fclamp-diagnostics.s
new file mode 100644
index 0000000000000..0bd3665412716
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/fclamp-diagnostics.s
@@ -0,0 +1,38 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+fclamp {z0.h-z2.h}, z0.h, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fclamp {z0.h-z2.h}, z0.h, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fclamp {z0.d-z4.d}, z5.d, z6.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+// CHECK-NEXT: fclamp {z0.d-z4.d}, z5.d, z6.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fclamp {z23.s-z24.s}, z13.s, z8.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element type
+// CHECK-NEXT: fclamp {z23.s-z24.s}, z13.s, z8.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fclamp {z21.h-z24.h}, z10.h, z21.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element type
+// CHECK-NEXT: fclamp {z21.h-z24.h}, z10.h, z21.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+fclamp {z0.h-z1.h}, z0.h, z4.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fclamp {z0.h-z1.h}, z0.h, z4.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fclamp {z0.s-z3.s}, z5.d, z6.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fclamp {z0.s-z3.s}, z5.d, z6.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2/fclamp.s b/llvm/test/MC/AArch64/SME2/fclamp.s
new file mode 100644
index 0000000000000..72c0627ffb3c4
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/fclamp.s
@@ -0,0 +1,163 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+fclamp {z0.d, z1.d}, z0.d, z0.d // 11000001-11100000-11000000-00000000
+// CHECK-INST: fclamp { z0.d, z1.d }, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0xc0,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0c000 <unknown>
+
+fclamp {z20.d, z21.d}, z10.d, z21.d // 11000001-11110101-11000001-01010100
+// CHECK-INST: fclamp { z20.d, z21.d }, z10.d, z21.d
+// CHECK-ENCODING: [0x54,0xc1,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f5c154 <unknown>
+
+fclamp {z22.d, z23.d}, z13.d, z8.d // 11000001-11101000-11000001-10110110
+// CHECK-INST: fclamp { z22.d, z23.d }, z13.d, z8.d
+// CHECK-ENCODING: [0xb6,0xc1,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8c1b6 <unknown>
+
+fclamp {z30.d, z31.d}, z31.d, z31.d // 11000001-11111111-11000011-11111110
+// CHECK-INST: fclamp { z30.d, z31.d }, z31.d, z31.d
+// CHECK-ENCODING: [0xfe,0xc3,0xff,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ffc3fe <unknown>
+
+
+fclamp {z0.h, z1.h}, z0.h, z0.h // 11000001-01100000-11000000-00000000
+// CHECK-INST: fclamp { z0.h, z1.h }, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0xc0,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160c000 <unknown>
+
+fclamp {z20.h, z21.h}, z10.h, z21.h // 11000001-01110101-11000001-01010100
+// CHECK-INST: fclamp { z20.h, z21.h }, z10.h, z21.h
+// CHECK-ENCODING: [0x54,0xc1,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c175c154 <unknown>
+
+fclamp {z22.h, z23.h}, z13.h, z8.h // 11000001-01101000-11000001-10110110
+// CHECK-INST: fclamp { z22.h, z23.h }, z13.h, z8.h
+// CHECK-ENCODING: [0xb6,0xc1,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168c1b6 <unknown>
+
+fclamp {z30.h, z31.h}, z31.h, z31.h // 11000001-01111111-11000011-11111110
+// CHECK-INST: fclamp { z30.h, z31.h }, z31.h, z31.h
+// CHECK-ENCODING: [0xfe,0xc3,0x7f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17fc3fe <unknown>
+
+
+fclamp {z0.s, z1.s}, z0.s, z0.s // 11000001-10100000-11000000-00000000
+// CHECK-INST: fclamp { z0.s, z1.s }, z0.s, z0.s
+// CHECK-ENCODING: [0x00,0xc0,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0c000 <unknown>
+
+fclamp {z20.s, z21.s}, z10.s, z21.s // 11000001-10110101-11000001-01010100
+// CHECK-INST: fclamp { z20.s, z21.s }, z10.s, z21.s
+// CHECK-ENCODING: [0x54,0xc1,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b5c154 <unknown>
+
+fclamp {z22.s, z23.s}, z13.s, z8.s // 11000001-10101000-11000001-10110110
+// CHECK-INST: fclamp { z22.s, z23.s }, z13.s, z8.s
+// CHECK-ENCODING: [0xb6,0xc1,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8c1b6 <unknown>
+
+fclamp {z30.s, z31.s}, z31.s, z31.s // 11000001-10111111-11000011-11111110
+// CHECK-INST: fclamp { z30.s, z31.s }, z31.s, z31.s
+// CHECK-ENCODING: [0xfe,0xc3,0xbf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bfc3fe <unknown>
+
+
+fclamp {z0.d - z3.d}, z0.d, z0.d // 11000001-11100000-11001000-00000000
+// CHECK-INST: fclamp { z0.d - z3.d }, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0xc8,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0c800 <unknown>
+
+fclamp {z20.d - z23.d}, z10.d, z21.d // 11000001-11110101-11001001-01010100
+// CHECK-INST: fclamp { z20.d - z23.d }, z10.d, z21.d
+// CHECK-ENCODING: [0x54,0xc9,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f5c954 <unknown>
+
+fclamp {z20.d - z23.d}, z13.d, z8.d // 11000001-11101000-11001001-10110100
+// CHECK-INST: fclamp { z20.d - z23.d }, z13.d, z8.d
+// CHECK-ENCODING: [0xb4,0xc9,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8c9b4 <unknown>
+
+fclamp {z28.d - z31.d}, z31.d, z31.d // 11000001-11111111-11001011-11111100
+// CHECK-INST: fclamp { z28.d - z31.d }, z31.d, z31.d
+// CHECK-ENCODING: [0xfc,0xcb,0xff,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ffcbfc <unknown>
+
+
+fclamp {z0.h - z3.h}, z0.h, z0.h // 11000001-01100000-11001000-00000000
+// CHECK-INST: fclamp { z0.h - z3.h }, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0xc8,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160c800 <unknown>
+
+fclamp {z20.h - z23.h}, z10.h, z21.h // 11000001-01110101-11001001-01010100
+// CHECK-INST: fclamp { z20.h - z23.h }, z10.h, z21.h
+// CHECK-ENCODING: [0x54,0xc9,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c175c954 <unknown>
+
+fclamp {z20.h - z23.h}, z13.h, z8.h // 11000001-01101000-11001001-10110100
+// CHECK-INST: fclamp { z20.h - z23.h }, z13.h, z8.h
+// CHECK-ENCODING: [0xb4,0xc9,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168c9b4 <unknown>
+
+fclamp {z28.h - z31.h}, z31.h, z31.h // 11000001-01111111-11001011-11111100
+// CHECK-INST: fclamp { z28.h - z31.h }, z31.h, z31.h
+// CHECK-ENCODING: [0xfc,0xcb,0x7f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17fcbfc <unknown>
+
+
+fclamp {z0.s - z3.s}, z0.s, z0.s // 11000001-10100000-11001000-00000000
+// CHECK-INST: fclamp { z0.s - z3.s }, z0.s, z0.s
+// CHECK-ENCODING: [0x00,0xc8,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0c800 <unknown>
+
+fclamp {z20.s - z23.s}, z10.s, z21.s // 11000001-10110101-11001001-01010100
+// CHECK-INST: fclamp { z20.s - z23.s }, z10.s, z21.s
+// CHECK-ENCODING: [0x54,0xc9,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b5c954 <unknown>
+
+fclamp {z20.s - z23.s}, z13.s, z8.s // 11000001-10101000-11001001-10110100
+// CHECK-INST: fclamp { z20.s - z23.s }, z13.s, z8.s
+// CHECK-ENCODING: [0xb4,0xc9,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8c9b4 <unknown>
+
+fclamp {z28.s - z31.s}, z31.s, z31.s // 11000001-10111111-11001011-11111100
+// CHECK-INST: fclamp { z28.s - z31.s }, z31.s, z31.s
+// CHECK-ENCODING: [0xfc,0xcb,0xbf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bfcbfc <unknown>
+
diff --git a/llvm/test/MC/AArch64/SME2/sclamp-diagnostics.s b/llvm/test/MC/AArch64/SME2/sclamp-diagnostics.s
new file mode 100644
index 0000000000000..cc60f3a550b46
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/sclamp-diagnostics.s
@@ -0,0 +1,22 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+sclamp {z0.b-z2.b}, z0.b, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: sclamp {z0.b-z2.b}, z0.b, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sclamp {z1.s-z2.s}, z0.s, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element type
+// CHECK-NEXT: sclamp {z1.s-z2.s}, z0.s, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+sclamp {z0.h-z1.h}, z0.h, z4.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sclamp {z0.h-z1.h}, z0.h, z4.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2/sclamp.s b/llvm/test/MC/AArch64/SME2/sclamp.s
new file mode 100644
index 0000000000000..8330519a0b717
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/sclamp.s
@@ -0,0 +1,213 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+sclamp {z0.h, z1.h}, z0.h, z0.h // 11000001-01100000-11000100-00000000
+// CHECK-INST: sclamp { z0.h, z1.h }, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0xc4,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160c400 <unknown>
+
+sclamp {z20.h, z21.h}, z10.h, z21.h // 11000001-01110101-11000101-01010100
+// CHECK-INST: sclamp { z20.h, z21.h }, z10.h, z21.h
+// CHECK-ENCODING: [0x54,0xc5,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c175c554 <unknown>
+
+sclamp {z22.h, z23.h}, z13.h, z8.h // 11000001-01101000-11000101-10110110
+// CHECK-INST: sclamp { z22.h, z23.h }, z13.h, z8.h
+// CHECK-ENCODING: [0xb6,0xc5,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168c5b6 <unknown>
+
+sclamp {z30.h, z31.h}, z31.h, z31.h // 11000001-01111111-11000111-11111110
+// CHECK-INST: sclamp { z30.h, z31.h }, z31.h, z31.h
+// CHECK-ENCODING: [0xfe,0xc7,0x7f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17fc7fe <unknown>
+
+
+sclamp {z0.s, z1.s}, z0.s, z0.s // 11000001-10100000-11000100-00000000
+// CHECK-INST: sclamp { z0.s, z1.s }, z0.s, z0.s
+// CHECK-ENCODING: [0x00,0xc4,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0c400 <unknown>
+
+sclamp {z20.s, z21.s}, z10.s, z21.s // 11000001-10110101-11000101-01010100
+// CHECK-INST: sclamp { z20.s, z21.s }, z10.s, z21.s
+// CHECK-ENCODING: [0x54,0xc5,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b5c554 <unknown>
+
+sclamp {z22.s, z23.s}, z13.s, z8.s // 11000001-10101000-11000101-10110110
+// CHECK-INST: sclamp { z22.s, z23.s }, z13.s, z8.s
+// CHECK-ENCODING: [0xb6,0xc5,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8c5b6 <unknown>
+
+sclamp {z30.s, z31.s}, z31.s, z31.s // 11000001-10111111-11000111-11111110
+// CHECK-INST: sclamp { z30.s, z31.s }, z31.s, z31.s
+// CHECK-ENCODING: [0xfe,0xc7,0xbf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bfc7fe <unknown>
+
+
+sclamp {z0.d, z1.d}, z0.d, z0.d // 11000001-11100000-11000100-00000000
+// CHECK-INST: sclamp { z0.d, z1.d }, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0xc4,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0c400 <unknown>
+
+sclamp {z20.d, z21.d}, z10.d, z21.d // 11000001-11110101-11000101-01010100
+// CHECK-INST: sclamp { z20.d, z21.d }, z10.d, z21.d
+// CHECK-ENCODING: [0x54,0xc5,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f5c554 <unknown>
+
+sclamp {z22.d, z23.d}, z13.d, z8.d // 11000001-11101000-11000101-10110110
+// CHECK-INST: sclamp { z22.d, z23.d }, z13.d, z8.d
+// CHECK-ENCODING: [0xb6,0xc5,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8c5b6 <unknown>
+
+sclamp {z30.d, z31.d}, z31.d, z31.d // 11000001-11111111-11000111-11111110
+// CHECK-INST: sclamp { z30.d, z31.d }, z31.d, z31.d
+// CHECK-ENCODING: [0xfe,0xc7,0xff,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ffc7fe <unknown>
+
+
+sclamp {z0.b, z1.b}, z0.b, z0.b // 11000001-00100000-11000100-00000000
+// CHECK-INST: sclamp { z0.b, z1.b }, z0.b, z0.b
+// CHECK-ENCODING: [0x00,0xc4,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120c400 <unknown>
+
+sclamp {z20.b, z21.b}, z10.b, z21.b // 11000001-00110101-11000101-01010100
+// CHECK-INST: sclamp { z20.b, z21.b }, z10.b, z21.b
+// CHECK-ENCODING: [0x54,0xc5,0x35,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c135c554 <unknown>
+
+sclamp {z22.b, z23.b}, z13.b, z8.b // 11000001-00101000-11000101-10110110
+// CHECK-INST: sclamp { z22.b, z23.b }, z13.b, z8.b
+// CHECK-ENCODING: [0xb6,0xc5,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128c5b6 <unknown>
+
+sclamp {z30.b, z31.b}, z31.b, z31.b // 11000001-00111111-11000111-11111110
+// CHECK-INST: sclamp { z30.b, z31.b }, z31.b, z31.b
+// CHECK-ENCODING: [0xfe,0xc7,0x3f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13fc7fe <unknown>
+
+
+sclamp {z0.h - z3.h}, z0.h, z0.h // 11000001-01100000-11001100-00000000
+// CHECK-INST: sclamp { z0.h - z3.h }, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0xcc,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160cc00 <unknown>
+
+sclamp {z20.h - z23.h}, z10.h, z21.h // 11000001-01110101-11001101-01010100
+// CHECK-INST: sclamp { z20.h - z23.h }, z10.h, z21.h
+// CHECK-ENCODING: [0x54,0xcd,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c175cd54 <unknown>
+
+sclamp {z20.h - z23.h}, z13.h, z8.h // 11000001-01101000-11001101-10110100
+// CHECK-INST: sclamp { z20.h - z23.h }, z13.h, z8.h
+// CHECK-ENCODING: [0xb4,0xcd,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168cdb4 <unknown>
+
+sclamp {z28.h - z31.h}, z31.h, z31.h // 11000001-01111111-11001111-11111100
+// CHECK-INST: sclamp { z28.h - z31.h }, z31.h, z31.h
+// CHECK-ENCODING: [0xfc,0xcf,0x7f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17fcffc <unknown>
+
+
+sclamp {z0.s - z3.s}, z0.s, z0.s // 11000001-10100000-11001100-00000000
+// CHECK-INST: sclamp { z0.s - z3.s }, z0.s, z0.s
+// CHECK-ENCODING: [0x00,0xcc,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0cc00 <unknown>
+
+sclamp {z20.s - z23.s}, z10.s, z21.s // 11000001-10110101-11001101-01010100
+// CHECK-INST: sclamp { z20.s - z23.s }, z10.s, z21.s
+// CHECK-ENCODING: [0x54,0xcd,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b5cd54 <unknown>
+
+sclamp {z20.s - z23.s}, z13.s, z8.s // 11000001-10101000-11001101-10110100
+// CHECK-INST: sclamp { z20.s - z23.s }, z13.s, z8.s
+// CHECK-ENCODING: [0xb4,0xcd,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8cdb4 <unknown>
+
+sclamp {z28.s - z31.s}, z31.s, z31.s // 11000001-10111111-11001111-11111100
+// CHECK-INST: sclamp { z28.s - z31.s }, z31.s, z31.s
+// CHECK-ENCODING: [0xfc,0xcf,0xbf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bfcffc <unknown>
+
+
+sclamp {z0.d - z3.d}, z0.d, z0.d // 11000001-11100000-11001100-00000000
+// CHECK-INST: sclamp { z0.d - z3.d }, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0xcc,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0cc00 <unknown>
+
+sclamp {z20.d - z23.d}, z10.d, z21.d // 11000001-11110101-11001101-01010100
+// CHECK-INST: sclamp { z20.d - z23.d }, z10.d, z21.d
+// CHECK-ENCODING: [0x54,0xcd,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f5cd54 <unknown>
+
+sclamp {z20.d - z23.d}, z13.d, z8.d // 11000001-11101000-11001101-10110100
+// CHECK-INST: sclamp { z20.d - z23.d }, z13.d, z8.d
+// CHECK-ENCODING: [0xb4,0xcd,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8cdb4 <unknown>
+
+sclamp {z28.d - z31.d}, z31.d, z31.d // 11000001-11111111-11001111-11111100
+// CHECK-INST: sclamp { z28.d - z31.d }, z31.d, z31.d
+// CHECK-ENCODING: [0xfc,0xcf,0xff,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ffcffc <unknown>
+
+
+sclamp {z0.b - z3.b}, z0.b, z0.b // 11000001-00100000-11001100-00000000
+// CHECK-INST: sclamp { z0.b - z3.b }, z0.b, z0.b
+// CHECK-ENCODING: [0x00,0xcc,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120cc00 <unknown>
+
+sclamp {z20.b - z23.b}, z10.b, z21.b // 11000001-00110101-11001101-01010100
+// CHECK-INST: sclamp { z20.b - z23.b }, z10.b, z21.b
+// CHECK-ENCODING: [0x54,0xcd,0x35,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c135cd54 <unknown>
+
+sclamp {z20.b - z23.b}, z13.b, z8.b // 11000001-00101000-11001101-10110100
+// CHECK-INST: sclamp { z20.b - z23.b }, z13.b, z8.b
+// CHECK-ENCODING: [0xb4,0xcd,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128cdb4 <unknown>
+
+sclamp {z28.b - z31.b}, z31.b, z31.b // 11000001-00111111-11001111-11111100
+// CHECK-INST: sclamp { z28.b - z31.b }, z31.b, z31.b
+// CHECK-ENCODING: [0xfc,0xcf,0x3f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13fcffc <unknown>
+
diff --git a/llvm/test/MC/AArch64/SME2/uclamp-diagnostics.s b/llvm/test/MC/AArch64/SME2/uclamp-diagnostics.s
new file mode 100644
index 0000000000000..5c52619badc16
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/uclamp-diagnostics.s
@@ -0,0 +1,22 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+uclamp {z0.b-z2.b}, z0.b, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: uclamp {z0.b-z2.b}, z0.b, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uclamp {z1.s-z2.s}, z0.s, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element type
+// CHECK-NEXT: uclamp {z1.s-z2.s}, z0.s, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+uclamp {z0.h-z1.h}, z0.h, z4.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: uclamp {z0.h-z1.h}, z0.h, z4.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2/uclamp.s b/llvm/test/MC/AArch64/SME2/uclamp.s
new file mode 100644
index 0000000000000..9391d53010838
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/uclamp.s
@@ -0,0 +1,213 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+uclamp {z0.h, z1.h}, z0.h, z0.h // 11000001-01100000-11000100-00000001
+// CHECK-INST: uclamp { z0.h, z1.h }, z0.h, z0.h
+// CHECK-ENCODING: [0x01,0xc4,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160c401 <unknown>
+
+uclamp {z20.h, z21.h}, z10.h, z21.h // 11000001-01110101-11000101-01010101
+// CHECK-INST: uclamp { z20.h, z21.h }, z10.h, z21.h
+// CHECK-ENCODING: [0x55,0xc5,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c175c555 <unknown>
+
+uclamp {z22.h, z23.h}, z13.h, z8.h // 11000001-01101000-11000101-10110111
+// CHECK-INST: uclamp { z22.h, z23.h }, z13.h, z8.h
+// CHECK-ENCODING: [0xb7,0xc5,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168c5b7 <unknown>
+
+uclamp {z30.h, z31.h}, z31.h, z31.h // 11000001-01111111-11000111-11111111
+// CHECK-INST: uclamp { z30.h, z31.h }, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0xc7,0x7f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17fc7ff <unknown>
+
+
+uclamp {z0.s, z1.s}, z0.s, z0.s // 11000001-10100000-11000100-00000001
+// CHECK-INST: uclamp { z0.s, z1.s }, z0.s, z0.s
+// CHECK-ENCODING: [0x01,0xc4,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0c401 <unknown>
+
+uclamp {z20.s, z21.s}, z10.s, z21.s // 11000001-10110101-11000101-01010101
+// CHECK-INST: uclamp { z20.s, z21.s }, z10.s, z21.s
+// CHECK-ENCODING: [0x55,0xc5,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b5c555 <unknown>
+
+uclamp {z22.s, z23.s}, z13.s, z8.s // 11000001-10101000-11000101-10110111
+// CHECK-INST: uclamp { z22.s, z23.s }, z13.s, z8.s
+// CHECK-ENCODING: [0xb7,0xc5,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8c5b7 <unknown>
+
+uclamp {z30.s, z31.s}, z31.s, z31.s // 11000001-10111111-11000111-11111111
+// CHECK-INST: uclamp { z30.s, z31.s }, z31.s, z31.s
+// CHECK-ENCODING: [0xff,0xc7,0xbf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bfc7ff <unknown>
+
+
+uclamp {z0.d, z1.d}, z0.d, z0.d // 11000001-11100000-11000100-00000001
+// CHECK-INST: uclamp { z0.d, z1.d }, z0.d, z0.d
+// CHECK-ENCODING: [0x01,0xc4,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0c401 <unknown>
+
+uclamp {z20.d, z21.d}, z10.d, z21.d // 11000001-11110101-11000101-01010101
+// CHECK-INST: uclamp { z20.d, z21.d }, z10.d, z21.d
+// CHECK-ENCODING: [0x55,0xc5,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f5c555 <unknown>
+
+uclamp {z22.d, z23.d}, z13.d, z8.d // 11000001-11101000-11000101-10110111
+// CHECK-INST: uclamp { z22.d, z23.d }, z13.d, z8.d
+// CHECK-ENCODING: [0xb7,0xc5,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8c5b7 <unknown>
+
+uclamp {z30.d, z31.d}, z31.d, z31.d // 11000001-11111111-11000111-11111111
+// CHECK-INST: uclamp { z30.d, z31.d }, z31.d, z31.d
+// CHECK-ENCODING: [0xff,0xc7,0xff,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ffc7ff <unknown>
+
+
+uclamp {z0.b, z1.b}, z0.b, z0.b // 11000001-00100000-11000100-00000001
+// CHECK-INST: uclamp { z0.b, z1.b }, z0.b, z0.b
+// CHECK-ENCODING: [0x01,0xc4,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120c401 <unknown>
+
+uclamp {z20.b, z21.b}, z10.b, z21.b // 11000001-00110101-11000101-01010101
+// CHECK-INST: uclamp { z20.b, z21.b }, z10.b, z21.b
+// CHECK-ENCODING: [0x55,0xc5,0x35,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c135c555 <unknown>
+
+uclamp {z22.b, z23.b}, z13.b, z8.b // 11000001-00101000-11000101-10110111
+// CHECK-INST: uclamp { z22.b, z23.b }, z13.b, z8.b
+// CHECK-ENCODING: [0xb7,0xc5,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128c5b7 <unknown>
+
+uclamp {z30.b, z31.b}, z31.b, z31.b // 11000001-00111111-11000111-11111111
+// CHECK-INST: uclamp { z30.b, z31.b }, z31.b, z31.b
+// CHECK-ENCODING: [0xff,0xc7,0x3f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13fc7ff <unknown>
+
+
+uclamp {z0.h - z3.h}, z0.h, z0.h // 11000001-01100000-11001100-00000001
+// CHECK-INST: uclamp { z0.h - z3.h }, z0.h, z0.h
+// CHECK-ENCODING: [0x01,0xcc,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160cc01 <unknown>
+
+uclamp {z20.h - z23.h}, z10.h, z21.h // 11000001-01110101-11001101-01010101
+// CHECK-INST: uclamp { z20.h - z23.h }, z10.h, z21.h
+// CHECK-ENCODING: [0x55,0xcd,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c175cd55 <unknown>
+
+uclamp {z20.h - z23.h}, z13.h, z8.h // 11000001-01101000-11001101-10110101
+// CHECK-INST: uclamp { z20.h - z23.h }, z13.h, z8.h
+// CHECK-ENCODING: [0xb5,0xcd,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168cdb5 <unknown>
+
+uclamp {z28.h - z31.h}, z31.h, z31.h // 11000001-01111111-11001111-11111101
+// CHECK-INST: uclamp { z28.h - z31.h }, z31.h, z31.h
+// CHECK-ENCODING: [0xfd,0xcf,0x7f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17fcffd <unknown>
+
+
+uclamp {z0.s - z3.s}, z0.s, z0.s // 11000001-10100000-11001100-00000001
+// CHECK-INST: uclamp { z0.s - z3.s }, z0.s, z0.s
+// CHECK-ENCODING: [0x01,0xcc,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0cc01 <unknown>
+
+uclamp {z20.s - z23.s}, z10.s, z21.s // 11000001-10110101-11001101-01010101
+// CHECK-INST: uclamp { z20.s - z23.s }, z10.s, z21.s
+// CHECK-ENCODING: [0x55,0xcd,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b5cd55 <unknown>
+
+uclamp {z20.s - z23.s}, z13.s, z8.s // 11000001-10101000-11001101-10110101
+// CHECK-INST: uclamp { z20.s - z23.s }, z13.s, z8.s
+// CHECK-ENCODING: [0xb5,0xcd,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8cdb5 <unknown>
+
+uclamp {z28.s - z31.s}, z31.s, z31.s // 11000001-10111111-11001111-11111101
+// CHECK-INST: uclamp { z28.s - z31.s }, z31.s, z31.s
+// CHECK-ENCODING: [0xfd,0xcf,0xbf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bfcffd <unknown>
+
+
+uclamp {z0.d - z3.d}, z0.d, z0.d // 11000001-11100000-11001100-00000001
+// CHECK-INST: uclamp { z0.d - z3.d }, z0.d, z0.d
+// CHECK-ENCODING: [0x01,0xcc,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0cc01 <unknown>
+
+uclamp {z20.d - z23.d}, z10.d, z21.d // 11000001-11110101-11001101-01010101
+// CHECK-INST: uclamp { z20.d - z23.d }, z10.d, z21.d
+// CHECK-ENCODING: [0x55,0xcd,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f5cd55 <unknown>
+
+uclamp {z20.d - z23.d}, z13.d, z8.d // 11000001-11101000-11001101-10110101
+// CHECK-INST: uclamp { z20.d - z23.d }, z13.d, z8.d
+// CHECK-ENCODING: [0xb5,0xcd,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8cdb5 <unknown>
+
+uclamp {z28.d - z31.d}, z31.d, z31.d // 11000001-11111111-11001111-11111101
+// CHECK-INST: uclamp { z28.d - z31.d }, z31.d, z31.d
+// CHECK-ENCODING: [0xfd,0xcf,0xff,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ffcffd <unknown>
+
+
+uclamp {z0.b - z3.b}, z0.b, z0.b // 11000001-00100000-11001100-00000001
+// CHECK-INST: uclamp { z0.b - z3.b }, z0.b, z0.b
+// CHECK-ENCODING: [0x01,0xcc,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120cc01 <unknown>
+
+uclamp {z20.b - z23.b}, z10.b, z21.b // 11000001-00110101-11001101-01010101
+// CHECK-INST: uclamp { z20.b - z23.b }, z10.b, z21.b
+// CHECK-ENCODING: [0x55,0xcd,0x35,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c135cd55 <unknown>
+
+uclamp {z20.b - z23.b}, z13.b, z8.b // 11000001-00101000-11001101-10110101
+// CHECK-INST: uclamp { z20.b - z23.b }, z13.b, z8.b
+// CHECK-ENCODING: [0xb5,0xcd,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128cdb5 <unknown>
+
+uclamp {z28.b - z31.b}, z31.b, z31.b // 11000001-00111111-11001111-11111101
+// CHECK-INST: uclamp { z28.b - z31.b }, z31.b, z31.b
+// CHECK-ENCODING: [0xfd,0xcf,0x3f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13fcffd <unknown>
+
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