[llvm] 021ed4c - [AArch64]SME2 Single and multiple vectors SVE Destructive two/four registers[part2]
Caroline Concatto via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 25 01:04:57 PDT 2022
Author: Caroline Concatto
Date: 2022-10-25T09:03:56+01:00
New Revision: 021ed4ccf61c83c487a804ec21a4f9bcb285faef
URL: https://github.com/llvm/llvm-project/commit/021ed4ccf61c83c487a804ec21a4f9bcb285faef
DIFF: https://github.com/llvm/llvm-project/commit/021ed4ccf61c83c487a804ec21a4f9bcb285faef.diff
LOG: [AArch64]SME2 Single and multiple vectors SVE Destructive two/four registers[part2]
This patch adds the assembly/disassembly for the following instruction:
INT:
SMAX (multiple and single vector): Multi-vector signed maximum by vector.
(multiple vectors): Multi-vector signed maximum.
SMIN (multiple and single vector): Multi-vector signed minimum by vector.
(multiple vectors): Multi-vector signed minimum.
UMAX (multiple and single vector): Multi-vector unsigned maximum by vector.
(multiple vectors): Multi-vector unsigned maximum.
UMIN (multiple and single vector): Multi-vector unsigned minimum by vector.
(multiple vectors): Multi-vector unsigned minimum.
SRSHL (multiple and single vector): Multi-vector signed rounding shift left by vector.
(multiple vectors): Multi-vector signed rounding shift left.
URSHL (multiple and single vector): Multi-vector unsigned rounding shift left by vector.
(multiple vectors): Multi-vector unsigned rounding shift left.
FP:
FMAX (multiple and single vector): Multi-vector floating-point maximum by vector.
(multiple vectors): Multi-vector floating-point maximum.
FMAXNM (multiple and single vector): Multi-vector floating-point maximum number by vector.
(multiple vectors): Multi-vector floating-point maximum number.
FMIN (multiple and single vector): Multi-vector floating-point minimum by vector.
(multiple vectors): Multi-vector floating-point minimum.
FMINNM (multiple and single vector): Multi-vector floating-point minimum number by vector.
(multiple vectors): Multi-vector floating-point minimum number.
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09
It also updates ADD and SQDMULH
Depends on: D135563
Differential Revision: https://reviews.llvm.org/D135599
Added:
llvm/test/MC/AArch64/SME2/fmax-diagnostics.s
llvm/test/MC/AArch64/SME2/fmax.s
llvm/test/MC/AArch64/SME2/fmaxnm-diagnostics.s
llvm/test/MC/AArch64/SME2/fmaxnm.s
llvm/test/MC/AArch64/SME2/fmin-diagnostics.s
llvm/test/MC/AArch64/SME2/fmin.s
llvm/test/MC/AArch64/SME2/fminnm-diagnostics.s
llvm/test/MC/AArch64/SME2/fminnm.s
llvm/test/MC/AArch64/SME2/smax-diagnostics.s
llvm/test/MC/AArch64/SME2/smax.s
llvm/test/MC/AArch64/SME2/smin-diagnostics.s
llvm/test/MC/AArch64/SME2/smin.s
llvm/test/MC/AArch64/SME2/srshl-diagnostics.s
llvm/test/MC/AArch64/SME2/srshl.s
llvm/test/MC/AArch64/SME2/umax-diagnostics.s
llvm/test/MC/AArch64/SME2/umax.s
llvm/test/MC/AArch64/SME2/umin-diagnostics.s
llvm/test/MC/AArch64/SME2/umin.s
llvm/test/MC/AArch64/SME2/urshl-diagnostics.s
llvm/test/MC/AArch64/SME2/urshl.s
Modified:
llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
llvm/lib/Target/AArch64/SMEInstrFormats.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
index 25d7d091c77ee..288915b784265 100644
--- a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
@@ -240,6 +240,9 @@ defm ADD_VG4_M4ZZ_S : sme2_mla_add_sub_array_vg4_single_S<"add", 0b10>;
defm ADD_VG2_M2Z2Z_S : sme2_mla_add_sub_array_vg2_multi_S<"add", 0b10>;
defm ADD_VG4_M4Z4Z_S : sme2_mla_add_sub_array_vg4_multi_S<"add", 0b10>;
+defm ADD_VG2_2ZZ : sme2_int_sve_destructive_vector_vg2_single<"add", 0b0110000>;
+defm ADD_VG4_4ZZ : sme2_int_sve_destructive_vector_vg4_single<"add", 0b0110000>;
+
defm SUB_VG2_M2ZZ_S : sme2_mla_add_sub_array_vg2_single_S<"sub", 0b11>;
defm SUB_VG4_M4ZZ_S : sme2_mla_add_sub_array_vg4_single_S<"sub", 0b11>;
defm SUB_VG2_M2Z2Z_S : sme2_mla_add_sub_array_vg2_multi_S<"sub", 0b11>;
@@ -254,10 +257,6 @@ defm FMLS_VG2_M2ZZ_S : sme2_mla_add_sub_array_vg2_single_S<"fmls", 0b01>;
defm FMLS_VG4_M4ZZ_S : sme2_mla_add_sub_array_vg4_single_S<"fmls", 0b01>;
defm FMLS_VG2_M2Z2Z_S : sme2_mla_add_sub_array_vg2_multi_S<"fmls", 0b01>;
defm FMLS_VG4_M4Z4Z_S : sme2_mla_add_sub_array_vg4_multi_S<"fmls", 0b01>;
-
-defm ADD_VG2_2ZZ : sme2_sqdmulh_add_vector_vg2_single<"add", 0b011000>;
-defm ADD_VG4_4ZZ : sme2_sqdmulh_add_vector_vg4_single<"add", 0b011000>;
-
defm ADDA_VG2_M2Z2Z_S : sme2_multivec_accum_add_sub_vg2_S<"add", 0b10>;
defm ADDA_VG4_M4Z4Z_S : sme2_multivec_accum_add_sub_vg4_S<"add", 0b10>;
@@ -270,10 +269,10 @@ defm FADD_VG4_M4Z4Z_S : sme2_multivec_accum_add_sub_vg4_S<"fadd", 0b00>;
defm FSUB_VG2_M2Z2Z_S : sme2_multivec_accum_add_sub_vg2_S<"fsub", 0b01>;
defm FSUB_VG4_M4Z4Z_S : sme2_multivec_accum_add_sub_vg4_S<"fsub", 0b01>;
-defm SQDMULH_2ZZ : sme2_sqdmulh_add_vector_vg2_single<"sqdmulh", 0b100000>;
-defm SQDMULH_4ZZ : sme2_sqdmulh_add_vector_vg4_single<"sqdmulh", 0b100000>;
-defm SQDMULH_2Z2Z2Z : sme2_sqdmulh_vector_vg2_multi<"sqdmulh">;
-defm SQDMULH_4Z4Z4Z : sme2_sqdmulh_vector_vg4_multi<"sqdmulh">;
+defm SQDMULH_VG2_2ZZ : sme2_int_sve_destructive_vector_vg2_single<"sqdmulh", 0b1000000>;
+defm SQDMULH_VG4_4ZZ : sme2_int_sve_destructive_vector_vg4_single<"sqdmulh", 0b1000000>;
+defm SQDMULH_VG2_2Z2Z : sme2_int_sve_destructive_vector_vg2_multi<"sqdmulh", 0b1000000>;
+defm SQDMULH_VG4_4Z4Z : sme2_int_sve_destructive_vector_vg4_multi<"sqdmulh", 0b1000000>;
defm FMLAL_MZZI : sme2_mla_long_array_index<"fmlal", 0b10, 0b00>;
defm FMLAL_VG2_M2ZZI : sme2_fp_mla_long_array_vg2_index<"fmlal", 0b00>;
@@ -371,6 +370,56 @@ def SCVTF_4Z4Z_StoS : sme2_fp_cvt_vg4_multi<"scvtf", 0b100>;
def UCVTF_2Z2Z_StoS : sme2_fp_cvt_vg2_multi<"ucvtf", 0b101>;
def UCVTF_4Z4Z_StoS : sme2_fp_cvt_vg4_multi<"ucvtf", 0b101>;
+defm SMAX_VG2_2ZZ : sme2_int_sve_destructive_vector_vg2_single<"smax", 0b0000000>;
+defm SMAX_VG4_4ZZ : sme2_int_sve_destructive_vector_vg4_single<"smax", 0b0000000>;
+defm SMAX_VG2_2Z2Z : sme2_int_sve_destructive_vector_vg2_multi<"smax", 0b0000000>;
+defm SMAX_VG4_4Z4Z : sme2_int_sve_destructive_vector_vg4_multi<"smax", 0b0000000>;
+
+defm UMAX_VG2_2ZZ : sme2_int_sve_destructive_vector_vg2_single<"umax", 0b0000001>;
+defm UMAX_VG4_4ZZ : sme2_int_sve_destructive_vector_vg4_single<"umax", 0b0000001>;
+defm UMAX_VG2_2Z2Z : sme2_int_sve_destructive_vector_vg2_multi<"umax", 0b0000001>;
+defm UMAX_VG4_4Z4Z : sme2_int_sve_destructive_vector_vg4_multi<"umax", 0b0000001>;
+
+defm SMIN_VG2_2ZZ : sme2_int_sve_destructive_vector_vg2_single<"smin", 0b0000010>;
+defm SMIN_VG4_4ZZ : sme2_int_sve_destructive_vector_vg4_single<"smin", 0b0000010>;
+defm SMIN_VG2_2Z2Z : sme2_int_sve_destructive_vector_vg2_multi<"smin", 0b0000010>;
+defm SMIN_VG4_4Z4Z : sme2_int_sve_destructive_vector_vg4_multi<"smin", 0b0000010>;
+
+defm UMIN_VG2_2ZZ : sme2_int_sve_destructive_vector_vg2_single<"umin", 0b0000011>;
+defm UMIN_VG4_4ZZ : sme2_int_sve_destructive_vector_vg4_single<"umin", 0b0000011>;
+defm UMIN_VG2_2Z2Z : sme2_int_sve_destructive_vector_vg2_multi<"umin", 0b0000011>;
+defm UMIN_VG4_4Z4Z : sme2_int_sve_destructive_vector_vg4_multi<"umin", 0b0000011>;
+
+defm FMAX_VG2_2ZZ : sme2_fp_sve_destructive_vector_vg2_single<"fmax", 0b0010000>;
+defm FMAX_VG4_4ZZ : sme2_fp_sve_destructive_vector_vg4_single<"fmax", 0b0010000>;
+defm FMAX_VG2_2Z2Z : sme2_fp_sve_destructive_vector_vg2_multi<"fmax", 0b0010000>;
+defm FMAX_VG4_4Z4Z : sme2_fp_sve_destructive_vector_vg4_multi<"fmax", 0b0010000>;
+
+defm FMIN_VG2_2ZZ : sme2_fp_sve_destructive_vector_vg2_single<"fmin", 0b0010001>;
+defm FMIN_VG4_4ZZ : sme2_fp_sve_destructive_vector_vg4_single<"fmin", 0b0010001>;
+defm FMIN_VG2_2Z2Z : sme2_fp_sve_destructive_vector_vg2_multi<"fmin", 0b0010001>;
+defm FMIN_VG4_4Z4Z : sme2_fp_sve_destructive_vector_vg4_multi<"fmin", 0b0010001>;
+
+defm FMAXNM_VG2_2ZZ : sme2_fp_sve_destructive_vector_vg2_single<"fmaxnm", 0b0010010>;
+defm FMAXNM_VG4_4ZZ : sme2_fp_sve_destructive_vector_vg4_single<"fmaxnm", 0b0010010>;
+defm FMAXNM_VG2_2Z2Z : sme2_fp_sve_destructive_vector_vg2_multi<"fmaxnm", 0b0010010>;
+defm FMAXNM_VG4_4Z4Z : sme2_fp_sve_destructive_vector_vg4_multi<"fmaxnm", 0b0010010>;
+
+defm FMINNM_VG2_2ZZ : sme2_fp_sve_destructive_vector_vg2_single<"fminnm", 0b0010011>;
+defm FMINNM_VG4_4ZZ : sme2_fp_sve_destructive_vector_vg4_single<"fminnm", 0b0010011>;
+defm FMINNM_VG2_2Z2Z : sme2_fp_sve_destructive_vector_vg2_multi<"fminnm", 0b0010011>;
+defm FMINNM_VG4_4Z4Z : sme2_fp_sve_destructive_vector_vg4_multi<"fminnm", 0b0010011>;
+
+defm SRSHL_VG2_2ZZ : sme2_int_sve_destructive_vector_vg2_single<"srshl", 0b0100010>;
+defm SRSHL_VG4_4ZZ : sme2_int_sve_destructive_vector_vg4_single<"srshl", 0b0100010>;
+defm SRSHL_VG2_2Z2Z : sme2_int_sve_destructive_vector_vg2_multi<"srshl", 0b0100010>;
+defm SRSHL_VG4_4Z4Z : sme2_int_sve_destructive_vector_vg4_multi<"srshl", 0b0100010>;
+
+defm URSHL_VG2_2ZZ : sme2_int_sve_destructive_vector_vg2_single<"urshl", 0b0100011>;
+defm URSHL_VG4_4ZZ : sme2_int_sve_destructive_vector_vg4_single<"urshl", 0b0100011>;
+defm URSHL_VG2_2Z2Z : sme2_int_sve_destructive_vector_vg2_multi<"urshl", 0b0100011>;
+defm URSHL_VG4_4Z4Z : sme2_int_sve_destructive_vector_vg4_multi<"urshl", 0b0100011>;
+
}
diff --git a/llvm/lib/Target/AArch64/SMEInstrFormats.td b/llvm/lib/Target/AArch64/SMEInstrFormats.td
index 53f781e00d856..0f4d3d52055db 100644
--- a/llvm/lib/Target/AArch64/SMEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SMEInstrFormats.td
@@ -1422,9 +1422,10 @@ multiclass sme2_multivec_accum_add_sub_vg4_D<string mnemonic, bits<2> op> {
// SME2 Multi-vector - Multiple and Single SVE Destructive
// Two and Four registers
-class sme2_sqdmulh_add_vector_vg2_single<bits<2> sz, bits<6> op,
- RegisterOperand vector_ty,
- ZPRRegOp zpr_ty, string mnemonic>
+class sme2_sve_destructive_vector_vg2_single<bits<2> sz, bits<7> op,
+ RegisterOperand vector_ty,
+ ZPRRegOp zpr_ty,
+ string mnemonic>
: I<(outs vector_ty:$Zdn), (ins vector_ty:$_Zdn, zpr_ty:$Zm),
mnemonic, "\t$Zdn, $_Zdn, $Zm",
"", []>, Sched<[]> {
@@ -1435,22 +1436,30 @@ class sme2_sqdmulh_add_vector_vg2_single<bits<2> sz, bits<6> op,
let Inst{21-20} = 0b10;
let Inst{19-16} = Zm;
let Inst{15-11} = 0b10100;
- let Inst{10-5} = op;
+ let Inst{10-5} = op{6-1};
let Inst{4-1} = Zdn;
- let Inst{0} = 0b0;
+ let Inst{0} = op{0};
+
let Constraints = "$Zdn = $_Zdn";
}
-multiclass sme2_sqdmulh_add_vector_vg2_single<string mnemonic, bits<6> op> {
- def _B : sme2_sqdmulh_add_vector_vg2_single<0b00, op, ZZ_b_mul_r, ZPR4b8, mnemonic>;
- def _H : sme2_sqdmulh_add_vector_vg2_single<0b01, op, ZZ_h_mul_r, ZPR4b16, mnemonic>;
- def _S : sme2_sqdmulh_add_vector_vg2_single<0b10, op, ZZ_s_mul_r, ZPR4b32, mnemonic>;
- def _D : sme2_sqdmulh_add_vector_vg2_single<0b11, op, ZZ_d_mul_r, ZPR4b64, mnemonic>;
+multiclass sme2_fp_sve_destructive_vector_vg2_single<string mnemonic, bits<7> op> {
+ def _H : sme2_sve_destructive_vector_vg2_single<0b01, op, ZZ_h_mul_r, ZPR4b16, mnemonic>;
+ def _S : sme2_sve_destructive_vector_vg2_single<0b10, op, ZZ_s_mul_r, ZPR4b32, mnemonic>;
+ def _D : sme2_sve_destructive_vector_vg2_single<0b11, op, ZZ_d_mul_r, ZPR4b64, mnemonic>;
}
-class sme2_sqdmulh_add_vector_vg4_single<bits<2> sz, bits<6> op,
- RegisterOperand vector_ty,
- ZPRRegOp zpr_ty, string mnemonic>
+multiclass sme2_int_sve_destructive_vector_vg2_single<string mnemonic, bits<7> op> {
+ def _B : sme2_sve_destructive_vector_vg2_single<0b00, op, ZZ_b_mul_r, ZPR4b8, mnemonic>;
+ def _H : sme2_sve_destructive_vector_vg2_single<0b01, op, ZZ_h_mul_r, ZPR4b16, mnemonic>;
+ def _S : sme2_sve_destructive_vector_vg2_single<0b10, op, ZZ_s_mul_r, ZPR4b32, mnemonic>;
+ def _D : sme2_sve_destructive_vector_vg2_single<0b11, op, ZZ_d_mul_r, ZPR4b64, mnemonic>;
+}
+
+class sme2_sve_destructive_vector_vg4_single<bits<2> sz, bits<7> op,
+ RegisterOperand vector_ty,
+ ZPRRegOp zpr_ty,
+ string mnemonic>
: I<(outs vector_ty:$Zdn), (ins vector_ty:$_Zdn, zpr_ty:$Zm),
mnemonic, "\t$Zdn, $_Zdn, $Zm",
"", []>, Sched<[]> {
@@ -1461,22 +1470,30 @@ class sme2_sqdmulh_add_vector_vg4_single<bits<2> sz, bits<6> op,
let Inst{21-20} = 0b10;
let Inst{19-16} = Zm;
let Inst{15-11} = 0b10101;
- let Inst{10-5} = op;
+ let Inst{10-5} = op{6-1};
let Inst{4-2} = Zdn;
- let Inst{1-0} = 0b00;
+ let Inst{1} = 0b0;
+ let Inst{0} = op{0};
+
let Constraints = "$Zdn = $_Zdn";
}
-multiclass sme2_sqdmulh_add_vector_vg4_single<string mnemonic, bits<6> op> {
- def _B : sme2_sqdmulh_add_vector_vg4_single<0b00, op, ZZZZ_b_mul_r, ZPR4b8, mnemonic>;
- def _H : sme2_sqdmulh_add_vector_vg4_single<0b01, op, ZZZZ_h_mul_r, ZPR4b16, mnemonic>;
- def _S : sme2_sqdmulh_add_vector_vg4_single<0b10, op, ZZZZ_s_mul_r, ZPR4b32, mnemonic>;
- def _D : sme2_sqdmulh_add_vector_vg4_single<0b11, op, ZZZZ_d_mul_r, ZPR4b64, mnemonic>;
+multiclass sme2_fp_sve_destructive_vector_vg4_single<string mnemonic, bits<7> op> {
+ def _H : sme2_sve_destructive_vector_vg4_single<0b01, op, ZZZZ_h_mul_r, ZPR4b16, mnemonic>;
+ def _S : sme2_sve_destructive_vector_vg4_single<0b10, op, ZZZZ_s_mul_r, ZPR4b32, mnemonic>;
+ def _D : sme2_sve_destructive_vector_vg4_single<0b11, op, ZZZZ_d_mul_r, ZPR4b64, mnemonic>;
}
+multiclass sme2_int_sve_destructive_vector_vg4_single<string mnemonic, bits<7> op> {
+ def _B : sme2_sve_destructive_vector_vg4_single<0b00, op, ZZZZ_b_mul_r, ZPR4b8, mnemonic>;
+ def _H : sme2_sve_destructive_vector_vg4_single<0b01, op, ZZZZ_h_mul_r, ZPR4b16, mnemonic>;
+ def _S : sme2_sve_destructive_vector_vg4_single<0b10, op, ZZZZ_s_mul_r, ZPR4b32, mnemonic>;
+ def _D : sme2_sve_destructive_vector_vg4_single<0b11, op, ZZZZ_d_mul_r, ZPR4b64, mnemonic>;
+}
-class sme2_sqdmulh_vector_vg2_multi<bits<2> sz, RegisterOperand vector_ty,
- string mnemonic>
+class sme2_sve_destructive_vector_vg2_multi<bits<2> sz, bits<7> op,
+ RegisterOperand vector_ty,
+ string mnemonic>
: I<(outs vector_ty:$Zdn), (ins vector_ty:$_Zdn, vector_ty:$Zm),
mnemonic, "\t$Zdn, $_Zdn, $Zm",
"", []>, Sched<[]> {
@@ -1486,21 +1503,30 @@ class sme2_sqdmulh_vector_vg2_multi<bits<2> sz, RegisterOperand vector_ty,
let Inst{23-22} = sz;
let Inst{21} = 0b1;
let Inst{20-17} = Zm;
- let Inst{16-5} = 0b010110100000;
+ let Inst{16-11} = 0b010110;
+ let Inst{10-5} = op{6-1};
let Inst{4-1} = Zdn;
- let Inst{0} = 0b0;
+ let Inst{0} = op{0};
+
let Constraints = "$Zdn = $_Zdn";
}
-multiclass sme2_sqdmulh_vector_vg2_multi<string mnemonic> {
- def _B : sme2_sqdmulh_vector_vg2_multi<0b00, ZZ_b_mul_r, mnemonic>;
- def _H : sme2_sqdmulh_vector_vg2_multi<0b01, ZZ_h_mul_r, mnemonic>;
- def _S : sme2_sqdmulh_vector_vg2_multi<0b10, ZZ_s_mul_r, mnemonic>;
- def _D : sme2_sqdmulh_vector_vg2_multi<0b11, ZZ_d_mul_r, mnemonic>;
+multiclass sme2_fp_sve_destructive_vector_vg2_multi<string mnemonic, bits<7> op> {
+ def _H : sme2_sve_destructive_vector_vg2_multi<0b01, op, ZZ_h_mul_r, mnemonic>;
+ def _S : sme2_sve_destructive_vector_vg2_multi<0b10, op, ZZ_s_mul_r, mnemonic>;
+ def _D : sme2_sve_destructive_vector_vg2_multi<0b11, op, ZZ_d_mul_r, mnemonic>;
+}
+
+multiclass sme2_int_sve_destructive_vector_vg2_multi<string mnemonic, bits<7> op> {
+ def _B : sme2_sve_destructive_vector_vg2_multi<0b00, op, ZZ_b_mul_r, mnemonic>;
+ def _H : sme2_sve_destructive_vector_vg2_multi<0b01, op, ZZ_h_mul_r, mnemonic>;
+ def _S : sme2_sve_destructive_vector_vg2_multi<0b10, op, ZZ_s_mul_r, mnemonic>;
+ def _D : sme2_sve_destructive_vector_vg2_multi<0b11, op, ZZ_d_mul_r, mnemonic>;
}
-class sme2_sqdmulh_vector_vg4_multi<bits<2> sz, RegisterOperand vector_ty,
- string mnemonic>
+class sme2_sve_destructive_vector_vg4_multi<bits<2> sz, bits<7> op,
+ RegisterOperand vector_ty,
+ string mnemonic>
: I<(outs vector_ty:$Zdn), (ins vector_ty:$_Zdn, vector_ty:$Zm),
mnemonic, "\t$Zdn, $_Zdn, $Zm",
"", []>, Sched<[]> {
@@ -1510,19 +1536,29 @@ class sme2_sqdmulh_vector_vg4_multi<bits<2> sz, RegisterOperand vector_ty,
let Inst{23-22} = sz;
let Inst{21} = 0b1;
let Inst{20-18} = Zm;
- let Inst{17-5} = 0b0010111100000;
+ let Inst{17-11} = 0b0010111;
+ let Inst{10-5} = op{6-1};
let Inst{4-2} = Zdn;
- let Inst{1-0} = 0b00;
+ let Inst{1} = 0b0;
+ let Inst{0} = op{0};
+
let Constraints = "$Zdn = $_Zdn";
}
-multiclass sme2_sqdmulh_vector_vg4_multi<string mnemonic> {
- def _B : sme2_sqdmulh_vector_vg4_multi<0b00, ZZZZ_b_mul_r, mnemonic>;
- def _H : sme2_sqdmulh_vector_vg4_multi<0b01, ZZZZ_h_mul_r, mnemonic>;
- def _S : sme2_sqdmulh_vector_vg4_multi<0b10, ZZZZ_s_mul_r, mnemonic>;
- def _D : sme2_sqdmulh_vector_vg4_multi<0b11, ZZZZ_d_mul_r, mnemonic>;
+multiclass sme2_fp_sve_destructive_vector_vg4_multi<string mnemonic, bits<7> op> {
+ def _H : sme2_sve_destructive_vector_vg4_multi<0b01, op, ZZZZ_h_mul_r, mnemonic>;
+ def _S : sme2_sve_destructive_vector_vg4_multi<0b10, op, ZZZZ_s_mul_r, mnemonic>;
+ def _D : sme2_sve_destructive_vector_vg4_multi<0b11, op, ZZZZ_d_mul_r, mnemonic>;
+}
+
+multiclass sme2_int_sve_destructive_vector_vg4_multi<string mnemonic, bits<7> op> {
+ def _B : sme2_sve_destructive_vector_vg4_multi<0b00, op, ZZZZ_b_mul_r, mnemonic>;
+ def _H : sme2_sve_destructive_vector_vg4_multi<0b01, op, ZZZZ_h_mul_r, mnemonic>;
+ def _S : sme2_sve_destructive_vector_vg4_multi<0b10, op, ZZZZ_s_mul_r, mnemonic>;
+ def _D : sme2_sve_destructive_vector_vg4_multi<0b11, op, ZZZZ_d_mul_r, mnemonic>;
}
+
//===----------------------------------------------------------------------===//
// SME2 Multi-vector - Index/Single/Multi Array Vectors FMA sources
diff --git a/llvm/test/MC/AArch64/SME2/fmax-diagnostics.s b/llvm/test/MC/AArch64/SME2/fmax-diagnostics.s
new file mode 100644
index 0000000000000..a2536bbb61dc5
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/fmax-diagnostics.s
@@ -0,0 +1,30 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+fmax {z0.d, z1.d}, {z0.d-z2.d}, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmax {z0.d, z1.d}, {z0.d-z2.d}, z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmax {z1.s-z2.s}, {z0.s, z1.s}, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element type
+// CHECK-NEXT: fmax {z1.s-z2.s}, {z0.s, z1.s}, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid single register
+
+fmax {z0.h, z1.h}, {z2.h-z3.h}, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: fmax {z0.h, z1.h}, {z2.h-z3.h}, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+fmax {z0.h, z1.h}, {z2.h-z3.h}, z14.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: fmax {z0.h, z1.h}, {z2.h-z3.h}, z14.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2/fmax.s b/llvm/test/MC/AArch64/SME2/fmax.s
new file mode 100644
index 0000000000000..71b8f1162f622
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/fmax.s
@@ -0,0 +1,313 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+fmax {z0.d, z1.d}, {z0.d, z1.d}, z0.d // 11000001-11100000-10100001-00000000
+// CHECK-INST: fmax { z0.d, z1.d }, { z0.d, z1.d }, z0.d
+// CHECK-ENCODING: [0x00,0xa1,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0a100 <unknown>
+
+fmax {z20.d, z21.d}, {z20.d, z21.d}, z5.d // 11000001-11100101-10100001-00010100
+// CHECK-INST: fmax { z20.d, z21.d }, { z20.d, z21.d }, z5.d
+// CHECK-ENCODING: [0x14,0xa1,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5a114 <unknown>
+
+fmax {z22.d, z23.d}, {z22.d, z23.d}, z8.d // 11000001-11101000-10100001-00010110
+// CHECK-INST: fmax { z22.d, z23.d }, { z22.d, z23.d }, z8.d
+// CHECK-ENCODING: [0x16,0xa1,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8a116 <unknown>
+
+fmax {z30.d, z31.d}, {z30.d, z31.d}, z15.d // 11000001-11101111-10100001-00011110
+// CHECK-INST: fmax { z30.d, z31.d }, { z30.d, z31.d }, z15.d
+// CHECK-ENCODING: [0x1e,0xa1,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efa11e <unknown>
+
+
+fmax {z0.d, z1.d}, {z0.d, z1.d}, {z0.d, z1.d} // 11000001-11100000-10110001-00000000
+// CHECK-INST: fmax { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }
+// CHECK-ENCODING: [0x00,0xb1,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0b100 <unknown>
+
+fmax {z20.d, z21.d}, {z20.d, z21.d}, {z20.d, z21.d} // 11000001-11110100-10110001-00010100
+// CHECK-INST: fmax { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }
+// CHECK-ENCODING: [0x14,0xb1,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4b114 <unknown>
+
+fmax {z22.d, z23.d}, {z22.d, z23.d}, {z8.d, z9.d} // 11000001-11101000-10110001-00010110
+// CHECK-INST: fmax { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }
+// CHECK-ENCODING: [0x16,0xb1,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8b116 <unknown>
+
+fmax {z30.d, z31.d}, {z30.d, z31.d}, {z30.d, z31.d} // 11000001-11111110-10110001-00011110
+// CHECK-INST: fmax { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0x1e,0xb1,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1feb11e <unknown>
+
+
+fmax {z0.h, z1.h}, {z0.h, z1.h}, z0.h // 11000001-01100000-10100001-00000000
+// CHECK-INST: fmax { z0.h, z1.h }, { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x00,0xa1,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160a100 <unknown>
+
+fmax {z20.h, z21.h}, {z20.h, z21.h}, z5.h // 11000001-01100101-10100001-00010100
+// CHECK-INST: fmax { z20.h, z21.h }, { z20.h, z21.h }, z5.h
+// CHECK-ENCODING: [0x14,0xa1,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165a114 <unknown>
+
+fmax {z22.h, z23.h}, {z22.h, z23.h}, z8.h // 11000001-01101000-10100001-00010110
+// CHECK-INST: fmax { z22.h, z23.h }, { z22.h, z23.h }, z8.h
+// CHECK-ENCODING: [0x16,0xa1,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168a116 <unknown>
+
+fmax {z30.h, z31.h}, {z30.h, z31.h}, z15.h // 11000001-01101111-10100001-00011110
+// CHECK-INST: fmax { z30.h, z31.h }, { z30.h, z31.h }, z15.h
+// CHECK-ENCODING: [0x1e,0xa1,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fa11e <unknown>
+
+
+fmax {z0.h, z1.h}, {z0.h, z1.h}, {z0.h, z1.h} // 11000001-01100000-10110001-00000000
+// CHECK-INST: fmax { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x00,0xb1,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160b100 <unknown>
+
+fmax {z20.h, z21.h}, {z20.h, z21.h}, {z20.h, z21.h} // 11000001-01110100-10110001-00010100
+// CHECK-INST: fmax { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x14,0xb1,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174b114 <unknown>
+
+fmax {z22.h, z23.h}, {z22.h, z23.h}, {z8.h, z9.h} // 11000001-01101000-10110001-00010110
+// CHECK-INST: fmax { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }
+// CHECK-ENCODING: [0x16,0xb1,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168b116 <unknown>
+
+fmax {z30.h, z31.h}, {z30.h, z31.h}, {z30.h, z31.h} // 11000001-01111110-10110001-00011110
+// CHECK-INST: fmax { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0x1e,0xb1,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17eb11e <unknown>
+
+
+fmax {z0.s, z1.s}, {z0.s, z1.s}, z0.s // 11000001-10100000-10100001-00000000
+// CHECK-INST: fmax { z0.s, z1.s }, { z0.s, z1.s }, z0.s
+// CHECK-ENCODING: [0x00,0xa1,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0a100 <unknown>
+
+fmax {z20.s, z21.s}, {z20.s, z21.s}, z5.s // 11000001-10100101-10100001-00010100
+// CHECK-INST: fmax { z20.s, z21.s }, { z20.s, z21.s }, z5.s
+// CHECK-ENCODING: [0x14,0xa1,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5a114 <unknown>
+
+fmax {z22.s, z23.s}, {z22.s, z23.s}, z8.s // 11000001-10101000-10100001-00010110
+// CHECK-INST: fmax { z22.s, z23.s }, { z22.s, z23.s }, z8.s
+// CHECK-ENCODING: [0x16,0xa1,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8a116 <unknown>
+
+fmax {z30.s, z31.s}, {z30.s, z31.s}, z15.s // 11000001-10101111-10100001-00011110
+// CHECK-INST: fmax { z30.s, z31.s }, { z30.s, z31.s }, z15.s
+// CHECK-ENCODING: [0x1e,0xa1,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afa11e <unknown>
+
+
+fmax {z0.s, z1.s}, {z0.s, z1.s}, {z0.s, z1.s} // 11000001-10100000-10110001-00000000
+// CHECK-INST: fmax { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x00,0xb1,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0b100 <unknown>
+
+fmax {z20.s, z21.s}, {z20.s, z21.s}, {z20.s, z21.s} // 11000001-10110100-10110001-00010100
+// CHECK-INST: fmax { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }
+// CHECK-ENCODING: [0x14,0xb1,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4b114 <unknown>
+
+fmax {z22.s, z23.s}, {z22.s, z23.s}, {z8.s, z9.s} // 11000001-10101000-10110001-00010110
+// CHECK-INST: fmax { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }
+// CHECK-ENCODING: [0x16,0xb1,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8b116 <unknown>
+
+fmax {z30.s, z31.s}, {z30.s, z31.s}, {z30.s, z31.s} // 11000001-10111110-10110001-00011110
+// CHECK-INST: fmax { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0x1e,0xb1,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1beb11e <unknown>
+
+
+fmax {z0.d - z3.d}, {z0.d - z3.d}, z0.d // 11000001-11100000-10101001-00000000
+// CHECK-INST: fmax { z0.d - z3.d }, { z0.d - z3.d }, z0.d
+// CHECK-ENCODING: [0x00,0xa9,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0a900 <unknown>
+
+fmax {z20.d - z23.d}, {z20.d - z23.d}, z5.d // 11000001-11100101-10101001-00010100
+// CHECK-INST: fmax { z20.d - z23.d }, { z20.d - z23.d }, z5.d
+// CHECK-ENCODING: [0x14,0xa9,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5a914 <unknown>
+
+fmax {z20.d - z23.d}, {z20.d - z23.d}, z8.d // 11000001-11101000-10101001-00010100
+// CHECK-INST: fmax { z20.d - z23.d }, { z20.d - z23.d }, z8.d
+// CHECK-ENCODING: [0x14,0xa9,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8a914 <unknown>
+
+fmax {z28.d - z31.d}, {z28.d - z31.d}, z15.d // 11000001-11101111-10101001-00011100
+// CHECK-INST: fmax { z28.d - z31.d }, { z28.d - z31.d }, z15.d
+// CHECK-ENCODING: [0x1c,0xa9,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efa91c <unknown>
+
+
+fmax {z0.d - z3.d}, {z0.d - z3.d}, {z0.d - z3.d} // 11000001-11100000-10111001-00000000
+// CHECK-INST: fmax { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x00,0xb9,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0b900 <unknown>
+
+fmax {z20.d - z23.d}, {z20.d - z23.d}, {z20.d - z23.d} // 11000001-11110100-10111001-00010100
+// CHECK-INST: fmax { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x14,0xb9,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4b914 <unknown>
+
+fmax {z20.d - z23.d}, {z20.d - z23.d}, {z8.d - z11.d} // 11000001-11101000-10111001-00010100
+// CHECK-INST: fmax { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x14,0xb9,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8b914 <unknown>
+
+fmax {z28.d - z31.d}, {z28.d - z31.d}, {z28.d - z31.d} // 11000001-11111100-10111001-00011100
+// CHECK-INST: fmax { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x1c,0xb9,0xfc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fcb91c <unknown>
+
+
+fmax {z0.h - z3.h}, {z0.h - z3.h}, z0.h // 11000001-01100000-10101001-00000000
+// CHECK-INST: fmax { z0.h - z3.h }, { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x00,0xa9,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160a900 <unknown>
+
+fmax {z20.h - z23.h}, {z20.h - z23.h}, z5.h // 11000001-01100101-10101001-00010100
+// CHECK-INST: fmax { z20.h - z23.h }, { z20.h - z23.h }, z5.h
+// CHECK-ENCODING: [0x14,0xa9,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165a914 <unknown>
+
+fmax {z20.h - z23.h}, {z20.h - z23.h}, z8.h // 11000001-01101000-10101001-00010100
+// CHECK-INST: fmax { z20.h - z23.h }, { z20.h - z23.h }, z8.h
+// CHECK-ENCODING: [0x14,0xa9,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168a914 <unknown>
+
+fmax {z28.h - z31.h}, {z28.h - z31.h}, z15.h // 11000001-01101111-10101001-00011100
+// CHECK-INST: fmax { z28.h - z31.h }, { z28.h - z31.h }, z15.h
+// CHECK-ENCODING: [0x1c,0xa9,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fa91c <unknown>
+
+
+fmax {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h} // 11000001-01100000-10111001-00000000
+// CHECK-INST: fmax { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x00,0xb9,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160b900 <unknown>
+
+fmax {z20.h - z23.h}, {z20.h - z23.h}, {z20.h - z23.h} // 11000001-01110100-10111001-00010100
+// CHECK-INST: fmax { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x14,0xb9,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174b914 <unknown>
+
+fmax {z20.h - z23.h}, {z20.h - z23.h}, {z8.h - z11.h} // 11000001-01101000-10111001-00010100
+// CHECK-INST: fmax { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x14,0xb9,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168b914 <unknown>
+
+fmax {z28.h - z31.h}, {z28.h - z31.h}, {z28.h - z31.h} // 11000001-01111100-10111001-00011100
+// CHECK-INST: fmax { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x1c,0xb9,0x7c,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17cb91c <unknown>
+
+
+fmax {z0.s - z3.s}, {z0.s - z3.s}, z0.s // 11000001-10100000-10101001-00000000
+// CHECK-INST: fmax { z0.s - z3.s }, { z0.s - z3.s }, z0.s
+// CHECK-ENCODING: [0x00,0xa9,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0a900 <unknown>
+
+fmax {z20.s - z23.s}, {z20.s - z23.s}, z5.s // 11000001-10100101-10101001-00010100
+// CHECK-INST: fmax { z20.s - z23.s }, { z20.s - z23.s }, z5.s
+// CHECK-ENCODING: [0x14,0xa9,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5a914 <unknown>
+
+fmax {z20.s - z23.s}, {z20.s - z23.s}, z8.s // 11000001-10101000-10101001-00010100
+// CHECK-INST: fmax { z20.s - z23.s }, { z20.s - z23.s }, z8.s
+// CHECK-ENCODING: [0x14,0xa9,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8a914 <unknown>
+
+fmax {z28.s - z31.s}, {z28.s - z31.s}, z15.s // 11000001-10101111-10101001-00011100
+// CHECK-INST: fmax { z28.s - z31.s }, { z28.s - z31.s }, z15.s
+// CHECK-ENCODING: [0x1c,0xa9,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afa91c <unknown>
+
+
+fmax {z0.s - z3.s}, {z0.s - z3.s}, {z0.s - z3.s} // 11000001-10100000-10111001-00000000
+// CHECK-INST: fmax { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x00,0xb9,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0b900 <unknown>
+
+fmax {z20.s - z23.s}, {z20.s - z23.s}, {z20.s - z23.s} // 11000001-10110100-10111001-00010100
+// CHECK-INST: fmax { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }
+// CHECK-ENCODING: [0x14,0xb9,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4b914 <unknown>
+
+fmax {z20.s - z23.s}, {z20.s - z23.s}, {z8.s - z11.s} // 11000001-10101000-10111001-00010100
+// CHECK-INST: fmax { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x14,0xb9,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8b914 <unknown>
+
+fmax {z28.s - z31.s}, {z28.s - z31.s}, {z28.s - z31.s} // 11000001-10111100-10111001-00011100
+// CHECK-INST: fmax { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x1c,0xb9,0xbc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bcb91c <unknown>
+
diff --git a/llvm/test/MC/AArch64/SME2/fmaxnm-diagnostics.s b/llvm/test/MC/AArch64/SME2/fmaxnm-diagnostics.s
new file mode 100644
index 0000000000000..9f667774c07cf
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/fmaxnm-diagnostics.s
@@ -0,0 +1,30 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+fmaxnm {z0.d, z1.d}, {z0.d-z2.d}, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmaxnm {z0.d, z1.d}, {z0.d-z2.d}, z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmaxnm {z1.s-z2.s}, {z0.s, z1.s}, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element type
+// CHECK-NEXT: fmaxnm {z1.s-z2.s}, {z0.s, z1.s}, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid single register
+
+fmaxnm {z0.h, z1.h}, {z2.h-z3.h}, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: fmaxnm {z0.h, z1.h}, {z2.h-z3.h}, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+fmaxnm {z0.h, z1.h}, {z2.h-z3.h}, z14.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: fmaxnm {z0.h, z1.h}, {z2.h-z3.h}, z14.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2/fmaxnm.s b/llvm/test/MC/AArch64/SME2/fmaxnm.s
new file mode 100644
index 0000000000000..6fa349ac40322
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/fmaxnm.s
@@ -0,0 +1,313 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+fmaxnm {z0.d, z1.d}, {z0.d, z1.d}, z0.d // 11000001-11100000-10100001-00100000
+// CHECK-INST: fmaxnm { z0.d, z1.d }, { z0.d, z1.d }, z0.d
+// CHECK-ENCODING: [0x20,0xa1,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0a120 <unknown>
+
+fmaxnm {z20.d, z21.d}, {z20.d, z21.d}, z5.d // 11000001-11100101-10100001-00110100
+// CHECK-INST: fmaxnm { z20.d, z21.d }, { z20.d, z21.d }, z5.d
+// CHECK-ENCODING: [0x34,0xa1,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5a134 <unknown>
+
+fmaxnm {z22.d, z23.d}, {z22.d, z23.d}, z8.d // 11000001-11101000-10100001-00110110
+// CHECK-INST: fmaxnm { z22.d, z23.d }, { z22.d, z23.d }, z8.d
+// CHECK-ENCODING: [0x36,0xa1,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8a136 <unknown>
+
+fmaxnm {z30.d, z31.d}, {z30.d, z31.d}, z15.d // 11000001-11101111-10100001-00111110
+// CHECK-INST: fmaxnm { z30.d, z31.d }, { z30.d, z31.d }, z15.d
+// CHECK-ENCODING: [0x3e,0xa1,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efa13e <unknown>
+
+
+fmaxnm {z0.d, z1.d}, {z0.d, z1.d}, {z0.d, z1.d} // 11000001-11100000-10110001-00100000
+// CHECK-INST: fmaxnm { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }
+// CHECK-ENCODING: [0x20,0xb1,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0b120 <unknown>
+
+fmaxnm {z20.d, z21.d}, {z20.d, z21.d}, {z20.d, z21.d} // 11000001-11110100-10110001-00110100
+// CHECK-INST: fmaxnm { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }
+// CHECK-ENCODING: [0x34,0xb1,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4b134 <unknown>
+
+fmaxnm {z22.d, z23.d}, {z22.d, z23.d}, {z8.d, z9.d} // 11000001-11101000-10110001-00110110
+// CHECK-INST: fmaxnm { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }
+// CHECK-ENCODING: [0x36,0xb1,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8b136 <unknown>
+
+fmaxnm {z30.d, z31.d}, {z30.d, z31.d}, {z30.d, z31.d} // 11000001-11111110-10110001-00111110
+// CHECK-INST: fmaxnm { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0x3e,0xb1,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1feb13e <unknown>
+
+
+fmaxnm {z0.h, z1.h}, {z0.h, z1.h}, z0.h // 11000001-01100000-10100001-00100000
+// CHECK-INST: fmaxnm { z0.h, z1.h }, { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x20,0xa1,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160a120 <unknown>
+
+fmaxnm {z20.h, z21.h}, {z20.h, z21.h}, z5.h // 11000001-01100101-10100001-00110100
+// CHECK-INST: fmaxnm { z20.h, z21.h }, { z20.h, z21.h }, z5.h
+// CHECK-ENCODING: [0x34,0xa1,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165a134 <unknown>
+
+fmaxnm {z22.h, z23.h}, {z22.h, z23.h}, z8.h // 11000001-01101000-10100001-00110110
+// CHECK-INST: fmaxnm { z22.h, z23.h }, { z22.h, z23.h }, z8.h
+// CHECK-ENCODING: [0x36,0xa1,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168a136 <unknown>
+
+fmaxnm {z30.h, z31.h}, {z30.h, z31.h}, z15.h // 11000001-01101111-10100001-00111110
+// CHECK-INST: fmaxnm { z30.h, z31.h }, { z30.h, z31.h }, z15.h
+// CHECK-ENCODING: [0x3e,0xa1,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fa13e <unknown>
+
+
+fmaxnm {z0.h, z1.h}, {z0.h, z1.h}, {z0.h, z1.h} // 11000001-01100000-10110001-00100000
+// CHECK-INST: fmaxnm { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x20,0xb1,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160b120 <unknown>
+
+fmaxnm {z20.h, z21.h}, {z20.h, z21.h}, {z20.h, z21.h} // 11000001-01110100-10110001-00110100
+// CHECK-INST: fmaxnm { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x34,0xb1,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174b134 <unknown>
+
+fmaxnm {z22.h, z23.h}, {z22.h, z23.h}, {z8.h, z9.h} // 11000001-01101000-10110001-00110110
+// CHECK-INST: fmaxnm { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }
+// CHECK-ENCODING: [0x36,0xb1,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168b136 <unknown>
+
+fmaxnm {z30.h, z31.h}, {z30.h, z31.h}, {z30.h, z31.h} // 11000001-01111110-10110001-00111110
+// CHECK-INST: fmaxnm { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0x3e,0xb1,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17eb13e <unknown>
+
+
+fmaxnm {z0.s, z1.s}, {z0.s, z1.s}, z0.s // 11000001-10100000-10100001-00100000
+// CHECK-INST: fmaxnm { z0.s, z1.s }, { z0.s, z1.s }, z0.s
+// CHECK-ENCODING: [0x20,0xa1,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0a120 <unknown>
+
+fmaxnm {z20.s, z21.s}, {z20.s, z21.s}, z5.s // 11000001-10100101-10100001-00110100
+// CHECK-INST: fmaxnm { z20.s, z21.s }, { z20.s, z21.s }, z5.s
+// CHECK-ENCODING: [0x34,0xa1,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5a134 <unknown>
+
+fmaxnm {z22.s, z23.s}, {z22.s, z23.s}, z8.s // 11000001-10101000-10100001-00110110
+// CHECK-INST: fmaxnm { z22.s, z23.s }, { z22.s, z23.s }, z8.s
+// CHECK-ENCODING: [0x36,0xa1,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8a136 <unknown>
+
+fmaxnm {z30.s, z31.s}, {z30.s, z31.s}, z15.s // 11000001-10101111-10100001-00111110
+// CHECK-INST: fmaxnm { z30.s, z31.s }, { z30.s, z31.s }, z15.s
+// CHECK-ENCODING: [0x3e,0xa1,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afa13e <unknown>
+
+
+fmaxnm {z0.s, z1.s}, {z0.s, z1.s}, {z0.s, z1.s} // 11000001-10100000-10110001-00100000
+// CHECK-INST: fmaxnm { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x20,0xb1,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0b120 <unknown>
+
+fmaxnm {z20.s, z21.s}, {z20.s, z21.s}, {z20.s, z21.s} // 11000001-10110100-10110001-00110100
+// CHECK-INST: fmaxnm { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }
+// CHECK-ENCODING: [0x34,0xb1,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4b134 <unknown>
+
+fmaxnm {z22.s, z23.s}, {z22.s, z23.s}, {z8.s, z9.s} // 11000001-10101000-10110001-00110110
+// CHECK-INST: fmaxnm { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }
+// CHECK-ENCODING: [0x36,0xb1,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8b136 <unknown>
+
+fmaxnm {z30.s, z31.s}, {z30.s, z31.s}, {z30.s, z31.s} // 11000001-10111110-10110001-00111110
+// CHECK-INST: fmaxnm { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0x3e,0xb1,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1beb13e <unknown>
+
+
+fmaxnm {z0.d - z3.d}, {z0.d - z3.d}, z0.d // 11000001-11100000-10101001-00100000
+// CHECK-INST: fmaxnm { z0.d - z3.d }, { z0.d - z3.d }, z0.d
+// CHECK-ENCODING: [0x20,0xa9,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0a920 <unknown>
+
+fmaxnm {z20.d - z23.d}, {z20.d - z23.d}, z5.d // 11000001-11100101-10101001-00110100
+// CHECK-INST: fmaxnm { z20.d - z23.d }, { z20.d - z23.d }, z5.d
+// CHECK-ENCODING: [0x34,0xa9,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5a934 <unknown>
+
+fmaxnm {z20.d - z23.d}, {z20.d - z23.d}, z8.d // 11000001-11101000-10101001-00110100
+// CHECK-INST: fmaxnm { z20.d - z23.d }, { z20.d - z23.d }, z8.d
+// CHECK-ENCODING: [0x34,0xa9,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8a934 <unknown>
+
+fmaxnm {z28.d - z31.d}, {z28.d - z31.d}, z15.d // 11000001-11101111-10101001-00111100
+// CHECK-INST: fmaxnm { z28.d - z31.d }, { z28.d - z31.d }, z15.d
+// CHECK-ENCODING: [0x3c,0xa9,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efa93c <unknown>
+
+
+fmaxnm {z0.d - z3.d}, {z0.d - z3.d}, {z0.d - z3.d} // 11000001-11100000-10111001-00100000
+// CHECK-INST: fmaxnm { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x20,0xb9,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0b920 <unknown>
+
+fmaxnm {z20.d - z23.d}, {z20.d - z23.d}, {z20.d - z23.d} // 11000001-11110100-10111001-00110100
+// CHECK-INST: fmaxnm { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x34,0xb9,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4b934 <unknown>
+
+fmaxnm {z20.d - z23.d}, {z20.d - z23.d}, {z8.d - z11.d} // 11000001-11101000-10111001-00110100
+// CHECK-INST: fmaxnm { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x34,0xb9,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8b934 <unknown>
+
+fmaxnm {z28.d - z31.d}, {z28.d - z31.d}, {z28.d - z31.d} // 11000001-11111100-10111001-00111100
+// CHECK-INST: fmaxnm { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x3c,0xb9,0xfc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fcb93c <unknown>
+
+
+fmaxnm {z0.h - z3.h}, {z0.h - z3.h}, z0.h // 11000001-01100000-10101001-00100000
+// CHECK-INST: fmaxnm { z0.h - z3.h }, { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x20,0xa9,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160a920 <unknown>
+
+fmaxnm {z20.h - z23.h}, {z20.h - z23.h}, z5.h // 11000001-01100101-10101001-00110100
+// CHECK-INST: fmaxnm { z20.h - z23.h }, { z20.h - z23.h }, z5.h
+// CHECK-ENCODING: [0x34,0xa9,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165a934 <unknown>
+
+fmaxnm {z20.h - z23.h}, {z20.h - z23.h}, z8.h // 11000001-01101000-10101001-00110100
+// CHECK-INST: fmaxnm { z20.h - z23.h }, { z20.h - z23.h }, z8.h
+// CHECK-ENCODING: [0x34,0xa9,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168a934 <unknown>
+
+fmaxnm {z28.h - z31.h}, {z28.h - z31.h}, z15.h // 11000001-01101111-10101001-00111100
+// CHECK-INST: fmaxnm { z28.h - z31.h }, { z28.h - z31.h }, z15.h
+// CHECK-ENCODING: [0x3c,0xa9,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fa93c <unknown>
+
+
+fmaxnm {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h} // 11000001-01100000-10111001-00100000
+// CHECK-INST: fmaxnm { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x20,0xb9,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160b920 <unknown>
+
+fmaxnm {z20.h - z23.h}, {z20.h - z23.h}, {z20.h - z23.h} // 11000001-01110100-10111001-00110100
+// CHECK-INST: fmaxnm { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x34,0xb9,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174b934 <unknown>
+
+fmaxnm {z20.h - z23.h}, {z20.h - z23.h}, {z8.h - z11.h} // 11000001-01101000-10111001-00110100
+// CHECK-INST: fmaxnm { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x34,0xb9,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168b934 <unknown>
+
+fmaxnm {z28.h - z31.h}, {z28.h - z31.h}, {z28.h - z31.h} // 11000001-01111100-10111001-00111100
+// CHECK-INST: fmaxnm { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x3c,0xb9,0x7c,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17cb93c <unknown>
+
+
+fmaxnm {z0.s - z3.s}, {z0.s - z3.s}, z0.s // 11000001-10100000-10101001-00100000
+// CHECK-INST: fmaxnm { z0.s - z3.s }, { z0.s - z3.s }, z0.s
+// CHECK-ENCODING: [0x20,0xa9,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0a920 <unknown>
+
+fmaxnm {z20.s - z23.s}, {z20.s - z23.s}, z5.s // 11000001-10100101-10101001-00110100
+// CHECK-INST: fmaxnm { z20.s - z23.s }, { z20.s - z23.s }, z5.s
+// CHECK-ENCODING: [0x34,0xa9,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5a934 <unknown>
+
+fmaxnm {z20.s - z23.s}, {z20.s - z23.s}, z8.s // 11000001-10101000-10101001-00110100
+// CHECK-INST: fmaxnm { z20.s - z23.s }, { z20.s - z23.s }, z8.s
+// CHECK-ENCODING: [0x34,0xa9,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8a934 <unknown>
+
+fmaxnm {z28.s - z31.s}, {z28.s - z31.s}, z15.s // 11000001-10101111-10101001-00111100
+// CHECK-INST: fmaxnm { z28.s - z31.s }, { z28.s - z31.s }, z15.s
+// CHECK-ENCODING: [0x3c,0xa9,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afa93c <unknown>
+
+
+fmaxnm {z0.s - z3.s}, {z0.s - z3.s}, {z0.s - z3.s} // 11000001-10100000-10111001-00100000
+// CHECK-INST: fmaxnm { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x20,0xb9,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0b920 <unknown>
+
+fmaxnm {z20.s - z23.s}, {z20.s - z23.s}, {z20.s - z23.s} // 11000001-10110100-10111001-00110100
+// CHECK-INST: fmaxnm { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }
+// CHECK-ENCODING: [0x34,0xb9,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4b934 <unknown>
+
+fmaxnm {z20.s - z23.s}, {z20.s - z23.s}, {z8.s - z11.s} // 11000001-10101000-10111001-00110100
+// CHECK-INST: fmaxnm { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x34,0xb9,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8b934 <unknown>
+
+fmaxnm {z28.s - z31.s}, {z28.s - z31.s}, {z28.s - z31.s} // 11000001-10111100-10111001-00111100
+// CHECK-INST: fmaxnm { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x3c,0xb9,0xbc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bcb93c <unknown>
+
diff --git a/llvm/test/MC/AArch64/SME2/fmin-diagnostics.s b/llvm/test/MC/AArch64/SME2/fmin-diagnostics.s
new file mode 100644
index 0000000000000..9b43161817486
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/fmin-diagnostics.s
@@ -0,0 +1,30 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+fmin {z0.d, z1.d}, {z0.d-z2.d}, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmin {z0.d, z1.d}, {z0.d-z2.d}, z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmin {z1.s-z2.s}, {z0.s, z1.s}, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element type
+// CHECK-NEXT: fmin {z1.s-z2.s}, {z0.s, z1.s}, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid single register
+
+fmin {z0.h, z1.h}, {z2.h-z3.h}, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: fmin {z0.h, z1.h}, {z2.h-z3.h}, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+fmin {z0.h, z1.h}, {z2.h-z3.h}, z14.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: fmin {z0.h, z1.h}, {z2.h-z3.h}, z14.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2/fmin.s b/llvm/test/MC/AArch64/SME2/fmin.s
new file mode 100644
index 0000000000000..56cecf13fe1b6
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/fmin.s
@@ -0,0 +1,313 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+fmin {z0.d, z1.d}, {z0.d, z1.d}, z0.d // 11000001-11100000-10100001-00000001
+// CHECK-INST: fmin { z0.d, z1.d }, { z0.d, z1.d }, z0.d
+// CHECK-ENCODING: [0x01,0xa1,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0a101 <unknown>
+
+fmin {z20.d, z21.d}, {z20.d, z21.d}, z5.d // 11000001-11100101-10100001-00010101
+// CHECK-INST: fmin { z20.d, z21.d }, { z20.d, z21.d }, z5.d
+// CHECK-ENCODING: [0x15,0xa1,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5a115 <unknown>
+
+fmin {z22.d, z23.d}, {z22.d, z23.d}, z8.d // 11000001-11101000-10100001-00010111
+// CHECK-INST: fmin { z22.d, z23.d }, { z22.d, z23.d }, z8.d
+// CHECK-ENCODING: [0x17,0xa1,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8a117 <unknown>
+
+fmin {z30.d, z31.d}, {z30.d, z31.d}, z15.d // 11000001-11101111-10100001-00011111
+// CHECK-INST: fmin { z30.d, z31.d }, { z30.d, z31.d }, z15.d
+// CHECK-ENCODING: [0x1f,0xa1,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efa11f <unknown>
+
+
+fmin {z0.d, z1.d}, {z0.d, z1.d}, {z0.d, z1.d} // 11000001-11100000-10110001-00000001
+// CHECK-INST: fmin { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }
+// CHECK-ENCODING: [0x01,0xb1,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0b101 <unknown>
+
+fmin {z20.d, z21.d}, {z20.d, z21.d}, {z20.d, z21.d} // 11000001-11110100-10110001-00010101
+// CHECK-INST: fmin { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }
+// CHECK-ENCODING: [0x15,0xb1,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4b115 <unknown>
+
+fmin {z22.d, z23.d}, {z22.d, z23.d}, {z8.d, z9.d} // 11000001-11101000-10110001-00010111
+// CHECK-INST: fmin { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }
+// CHECK-ENCODING: [0x17,0xb1,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8b117 <unknown>
+
+fmin {z30.d, z31.d}, {z30.d, z31.d}, {z30.d, z31.d} // 11000001-11111110-10110001-00011111
+// CHECK-INST: fmin { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0x1f,0xb1,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1feb11f <unknown>
+
+
+fmin {z0.h, z1.h}, {z0.h, z1.h}, z0.h // 11000001-01100000-10100001-00000001
+// CHECK-INST: fmin { z0.h, z1.h }, { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x01,0xa1,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160a101 <unknown>
+
+fmin {z20.h, z21.h}, {z20.h, z21.h}, z5.h // 11000001-01100101-10100001-00010101
+// CHECK-INST: fmin { z20.h, z21.h }, { z20.h, z21.h }, z5.h
+// CHECK-ENCODING: [0x15,0xa1,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165a115 <unknown>
+
+fmin {z22.h, z23.h}, {z22.h, z23.h}, z8.h // 11000001-01101000-10100001-00010111
+// CHECK-INST: fmin { z22.h, z23.h }, { z22.h, z23.h }, z8.h
+// CHECK-ENCODING: [0x17,0xa1,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168a117 <unknown>
+
+fmin {z30.h, z31.h}, {z30.h, z31.h}, z15.h // 11000001-01101111-10100001-00011111
+// CHECK-INST: fmin { z30.h, z31.h }, { z30.h, z31.h }, z15.h
+// CHECK-ENCODING: [0x1f,0xa1,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fa11f <unknown>
+
+
+fmin {z0.h, z1.h}, {z0.h, z1.h}, {z0.h, z1.h} // 11000001-01100000-10110001-00000001
+// CHECK-INST: fmin { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x01,0xb1,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160b101 <unknown>
+
+fmin {z20.h, z21.h}, {z20.h, z21.h}, {z20.h, z21.h} // 11000001-01110100-10110001-00010101
+// CHECK-INST: fmin { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x15,0xb1,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174b115 <unknown>
+
+fmin {z22.h, z23.h}, {z22.h, z23.h}, {z8.h, z9.h} // 11000001-01101000-10110001-00010111
+// CHECK-INST: fmin { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }
+// CHECK-ENCODING: [0x17,0xb1,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168b117 <unknown>
+
+fmin {z30.h, z31.h}, {z30.h, z31.h}, {z30.h, z31.h} // 11000001-01111110-10110001-00011111
+// CHECK-INST: fmin { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0x1f,0xb1,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17eb11f <unknown>
+
+
+fmin {z0.s, z1.s}, {z0.s, z1.s}, z0.s // 11000001-10100000-10100001-00000001
+// CHECK-INST: fmin { z0.s, z1.s }, { z0.s, z1.s }, z0.s
+// CHECK-ENCODING: [0x01,0xa1,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0a101 <unknown>
+
+fmin {z20.s, z21.s}, {z20.s, z21.s}, z5.s // 11000001-10100101-10100001-00010101
+// CHECK-INST: fmin { z20.s, z21.s }, { z20.s, z21.s }, z5.s
+// CHECK-ENCODING: [0x15,0xa1,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5a115 <unknown>
+
+fmin {z22.s, z23.s}, {z22.s, z23.s}, z8.s // 11000001-10101000-10100001-00010111
+// CHECK-INST: fmin { z22.s, z23.s }, { z22.s, z23.s }, z8.s
+// CHECK-ENCODING: [0x17,0xa1,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8a117 <unknown>
+
+fmin {z30.s, z31.s}, {z30.s, z31.s}, z15.s // 11000001-10101111-10100001-00011111
+// CHECK-INST: fmin { z30.s, z31.s }, { z30.s, z31.s }, z15.s
+// CHECK-ENCODING: [0x1f,0xa1,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afa11f <unknown>
+
+
+fmin {z0.s, z1.s}, {z0.s, z1.s}, {z0.s, z1.s} // 11000001-10100000-10110001-00000001
+// CHECK-INST: fmin { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x01,0xb1,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0b101 <unknown>
+
+fmin {z20.s, z21.s}, {z20.s, z21.s}, {z20.s, z21.s} // 11000001-10110100-10110001-00010101
+// CHECK-INST: fmin { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }
+// CHECK-ENCODING: [0x15,0xb1,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4b115 <unknown>
+
+fmin {z22.s, z23.s}, {z22.s, z23.s}, {z8.s, z9.s} // 11000001-10101000-10110001-00010111
+// CHECK-INST: fmin { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }
+// CHECK-ENCODING: [0x17,0xb1,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8b117 <unknown>
+
+fmin {z30.s, z31.s}, {z30.s, z31.s}, {z30.s, z31.s} // 11000001-10111110-10110001-00011111
+// CHECK-INST: fmin { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0x1f,0xb1,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1beb11f <unknown>
+
+
+fmin {z0.d - z3.d}, {z0.d - z3.d}, z0.d // 11000001-11100000-10101001-00000001
+// CHECK-INST: fmin { z0.d - z3.d }, { z0.d - z3.d }, z0.d
+// CHECK-ENCODING: [0x01,0xa9,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0a901 <unknown>
+
+fmin {z20.d - z23.d}, {z20.d - z23.d}, z5.d // 11000001-11100101-10101001-00010101
+// CHECK-INST: fmin { z20.d - z23.d }, { z20.d - z23.d }, z5.d
+// CHECK-ENCODING: [0x15,0xa9,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5a915 <unknown>
+
+fmin {z20.d - z23.d}, {z20.d - z23.d}, z8.d // 11000001-11101000-10101001-00010101
+// CHECK-INST: fmin { z20.d - z23.d }, { z20.d - z23.d }, z8.d
+// CHECK-ENCODING: [0x15,0xa9,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8a915 <unknown>
+
+fmin {z28.d - z31.d}, {z28.d - z31.d}, z15.d // 11000001-11101111-10101001-00011101
+// CHECK-INST: fmin { z28.d - z31.d }, { z28.d - z31.d }, z15.d
+// CHECK-ENCODING: [0x1d,0xa9,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efa91d <unknown>
+
+
+fmin {z0.d - z3.d}, {z0.d - z3.d}, {z0.d - z3.d} // 11000001-11100000-10111001-00000001
+// CHECK-INST: fmin { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x01,0xb9,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0b901 <unknown>
+
+fmin {z20.d - z23.d}, {z20.d - z23.d}, {z20.d - z23.d} // 11000001-11110100-10111001-00010101
+// CHECK-INST: fmin { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x15,0xb9,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4b915 <unknown>
+
+fmin {z20.d - z23.d}, {z20.d - z23.d}, {z8.d - z11.d} // 11000001-11101000-10111001-00010101
+// CHECK-INST: fmin { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x15,0xb9,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8b915 <unknown>
+
+fmin {z28.d - z31.d}, {z28.d - z31.d}, {z28.d - z31.d} // 11000001-11111100-10111001-00011101
+// CHECK-INST: fmin { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x1d,0xb9,0xfc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fcb91d <unknown>
+
+
+fmin {z0.h - z3.h}, {z0.h - z3.h}, z0.h // 11000001-01100000-10101001-00000001
+// CHECK-INST: fmin { z0.h - z3.h }, { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x01,0xa9,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160a901 <unknown>
+
+fmin {z20.h - z23.h}, {z20.h - z23.h}, z5.h // 11000001-01100101-10101001-00010101
+// CHECK-INST: fmin { z20.h - z23.h }, { z20.h - z23.h }, z5.h
+// CHECK-ENCODING: [0x15,0xa9,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165a915 <unknown>
+
+fmin {z20.h - z23.h}, {z20.h - z23.h}, z8.h // 11000001-01101000-10101001-00010101
+// CHECK-INST: fmin { z20.h - z23.h }, { z20.h - z23.h }, z8.h
+// CHECK-ENCODING: [0x15,0xa9,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168a915 <unknown>
+
+fmin {z28.h - z31.h}, {z28.h - z31.h}, z15.h // 11000001-01101111-10101001-00011101
+// CHECK-INST: fmin { z28.h - z31.h }, { z28.h - z31.h }, z15.h
+// CHECK-ENCODING: [0x1d,0xa9,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fa91d <unknown>
+
+
+fmin {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h} // 11000001-01100000-10111001-00000001
+// CHECK-INST: fmin { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x01,0xb9,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160b901 <unknown>
+
+fmin {z20.h - z23.h}, {z20.h - z23.h}, {z20.h - z23.h} // 11000001-01110100-10111001-00010101
+// CHECK-INST: fmin { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x15,0xb9,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174b915 <unknown>
+
+fmin {z20.h - z23.h}, {z20.h - z23.h}, {z8.h - z11.h} // 11000001-01101000-10111001-00010101
+// CHECK-INST: fmin { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x15,0xb9,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168b915 <unknown>
+
+fmin {z28.h - z31.h}, {z28.h - z31.h}, {z28.h - z31.h} // 11000001-01111100-10111001-00011101
+// CHECK-INST: fmin { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x1d,0xb9,0x7c,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17cb91d <unknown>
+
+
+fmin {z0.s - z3.s}, {z0.s - z3.s}, z0.s // 11000001-10100000-10101001-00000001
+// CHECK-INST: fmin { z0.s - z3.s }, { z0.s - z3.s }, z0.s
+// CHECK-ENCODING: [0x01,0xa9,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0a901 <unknown>
+
+fmin {z20.s - z23.s}, {z20.s - z23.s}, z5.s // 11000001-10100101-10101001-00010101
+// CHECK-INST: fmin { z20.s - z23.s }, { z20.s - z23.s }, z5.s
+// CHECK-ENCODING: [0x15,0xa9,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5a915 <unknown>
+
+fmin {z20.s - z23.s}, {z20.s - z23.s}, z8.s // 11000001-10101000-10101001-00010101
+// CHECK-INST: fmin { z20.s - z23.s }, { z20.s - z23.s }, z8.s
+// CHECK-ENCODING: [0x15,0xa9,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8a915 <unknown>
+
+fmin {z28.s - z31.s}, {z28.s - z31.s}, z15.s // 11000001-10101111-10101001-00011101
+// CHECK-INST: fmin { z28.s - z31.s }, { z28.s - z31.s }, z15.s
+// CHECK-ENCODING: [0x1d,0xa9,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afa91d <unknown>
+
+
+fmin {z0.s - z3.s}, {z0.s - z3.s}, {z0.s - z3.s} // 11000001-10100000-10111001-00000001
+// CHECK-INST: fmin { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x01,0xb9,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0b901 <unknown>
+
+fmin {z20.s - z23.s}, {z20.s - z23.s}, {z20.s - z23.s} // 11000001-10110100-10111001-00010101
+// CHECK-INST: fmin { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }
+// CHECK-ENCODING: [0x15,0xb9,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4b915 <unknown>
+
+fmin {z20.s - z23.s}, {z20.s - z23.s}, {z8.s - z11.s} // 11000001-10101000-10111001-00010101
+// CHECK-INST: fmin { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x15,0xb9,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8b915 <unknown>
+
+fmin {z28.s - z31.s}, {z28.s - z31.s}, {z28.s - z31.s} // 11000001-10111100-10111001-00011101
+// CHECK-INST: fmin { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x1d,0xb9,0xbc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bcb91d <unknown>
+
diff --git a/llvm/test/MC/AArch64/SME2/fminnm-diagnostics.s b/llvm/test/MC/AArch64/SME2/fminnm-diagnostics.s
new file mode 100644
index 0000000000000..9e320db6ddd23
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/fminnm-diagnostics.s
@@ -0,0 +1,30 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+fminnm {z0.d, z1.d}, {z0.d-z2.d}, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fminnm {z0.d, z1.d}, {z0.d-z2.d}, z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fminnm {z1.s-z2.s}, {z0.s, z1.s}, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element type
+// CHECK-NEXT: fminnm {z1.s-z2.s}, {z0.s, z1.s}, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid single register
+
+fminnm {z0.h, z1.h}, {z2.h-z3.h}, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: fminnm {z0.h, z1.h}, {z2.h-z3.h}, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+fminnm {z0.h, z1.h}, {z2.h-z3.h}, z14.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: fminnm {z0.h, z1.h}, {z2.h-z3.h}, z14.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2/fminnm.s b/llvm/test/MC/AArch64/SME2/fminnm.s
new file mode 100644
index 0000000000000..a16442dd505d0
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/fminnm.s
@@ -0,0 +1,313 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+fminnm {z0.d, z1.d}, {z0.d, z1.d}, z0.d // 11000001-11100000-10100001-00100001
+// CHECK-INST: fminnm { z0.d, z1.d }, { z0.d, z1.d }, z0.d
+// CHECK-ENCODING: [0x21,0xa1,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0a121 <unknown>
+
+fminnm {z20.d, z21.d}, {z20.d, z21.d}, z5.d // 11000001-11100101-10100001-00110101
+// CHECK-INST: fminnm { z20.d, z21.d }, { z20.d, z21.d }, z5.d
+// CHECK-ENCODING: [0x35,0xa1,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5a135 <unknown>
+
+fminnm {z22.d, z23.d}, {z22.d, z23.d}, z8.d // 11000001-11101000-10100001-00110111
+// CHECK-INST: fminnm { z22.d, z23.d }, { z22.d, z23.d }, z8.d
+// CHECK-ENCODING: [0x37,0xa1,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8a137 <unknown>
+
+fminnm {z30.d, z31.d}, {z30.d, z31.d}, z15.d // 11000001-11101111-10100001-00111111
+// CHECK-INST: fminnm { z30.d, z31.d }, { z30.d, z31.d }, z15.d
+// CHECK-ENCODING: [0x3f,0xa1,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efa13f <unknown>
+
+
+fminnm {z0.d, z1.d}, {z0.d, z1.d}, {z0.d, z1.d} // 11000001-11100000-10110001-00100001
+// CHECK-INST: fminnm { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }
+// CHECK-ENCODING: [0x21,0xb1,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0b121 <unknown>
+
+fminnm {z20.d, z21.d}, {z20.d, z21.d}, {z20.d, z21.d} // 11000001-11110100-10110001-00110101
+// CHECK-INST: fminnm { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }
+// CHECK-ENCODING: [0x35,0xb1,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4b135 <unknown>
+
+fminnm {z22.d, z23.d}, {z22.d, z23.d}, {z8.d, z9.d} // 11000001-11101000-10110001-00110111
+// CHECK-INST: fminnm { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }
+// CHECK-ENCODING: [0x37,0xb1,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8b137 <unknown>
+
+fminnm {z30.d, z31.d}, {z30.d, z31.d}, {z30.d, z31.d} // 11000001-11111110-10110001-00111111
+// CHECK-INST: fminnm { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0x3f,0xb1,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1feb13f <unknown>
+
+
+fminnm {z0.h, z1.h}, {z0.h, z1.h}, z0.h // 11000001-01100000-10100001-00100001
+// CHECK-INST: fminnm { z0.h, z1.h }, { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x21,0xa1,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160a121 <unknown>
+
+fminnm {z20.h, z21.h}, {z20.h, z21.h}, z5.h // 11000001-01100101-10100001-00110101
+// CHECK-INST: fminnm { z20.h, z21.h }, { z20.h, z21.h }, z5.h
+// CHECK-ENCODING: [0x35,0xa1,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165a135 <unknown>
+
+fminnm {z22.h, z23.h}, {z22.h, z23.h}, z8.h // 11000001-01101000-10100001-00110111
+// CHECK-INST: fminnm { z22.h, z23.h }, { z22.h, z23.h }, z8.h
+// CHECK-ENCODING: [0x37,0xa1,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168a137 <unknown>
+
+fminnm {z30.h, z31.h}, {z30.h, z31.h}, z15.h // 11000001-01101111-10100001-00111111
+// CHECK-INST: fminnm { z30.h, z31.h }, { z30.h, z31.h }, z15.h
+// CHECK-ENCODING: [0x3f,0xa1,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fa13f <unknown>
+
+
+fminnm {z0.h, z1.h}, {z0.h, z1.h}, {z0.h, z1.h} // 11000001-01100000-10110001-00100001
+// CHECK-INST: fminnm { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x21,0xb1,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160b121 <unknown>
+
+fminnm {z20.h, z21.h}, {z20.h, z21.h}, {z20.h, z21.h} // 11000001-01110100-10110001-00110101
+// CHECK-INST: fminnm { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x35,0xb1,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174b135 <unknown>
+
+fminnm {z22.h, z23.h}, {z22.h, z23.h}, {z8.h, z9.h} // 11000001-01101000-10110001-00110111
+// CHECK-INST: fminnm { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }
+// CHECK-ENCODING: [0x37,0xb1,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168b137 <unknown>
+
+fminnm {z30.h, z31.h}, {z30.h, z31.h}, {z30.h, z31.h} // 11000001-01111110-10110001-00111111
+// CHECK-INST: fminnm { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0x3f,0xb1,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17eb13f <unknown>
+
+
+fminnm {z0.s, z1.s}, {z0.s, z1.s}, z0.s // 11000001-10100000-10100001-00100001
+// CHECK-INST: fminnm { z0.s, z1.s }, { z0.s, z1.s }, z0.s
+// CHECK-ENCODING: [0x21,0xa1,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0a121 <unknown>
+
+fminnm {z20.s, z21.s}, {z20.s, z21.s}, z5.s // 11000001-10100101-10100001-00110101
+// CHECK-INST: fminnm { z20.s, z21.s }, { z20.s, z21.s }, z5.s
+// CHECK-ENCODING: [0x35,0xa1,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5a135 <unknown>
+
+fminnm {z22.s, z23.s}, {z22.s, z23.s}, z8.s // 11000001-10101000-10100001-00110111
+// CHECK-INST: fminnm { z22.s, z23.s }, { z22.s, z23.s }, z8.s
+// CHECK-ENCODING: [0x37,0xa1,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8a137 <unknown>
+
+fminnm {z30.s, z31.s}, {z30.s, z31.s}, z15.s // 11000001-10101111-10100001-00111111
+// CHECK-INST: fminnm { z30.s, z31.s }, { z30.s, z31.s }, z15.s
+// CHECK-ENCODING: [0x3f,0xa1,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afa13f <unknown>
+
+
+fminnm {z0.s, z1.s}, {z0.s, z1.s}, {z0.s, z1.s} // 11000001-10100000-10110001-00100001
+// CHECK-INST: fminnm { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x21,0xb1,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0b121 <unknown>
+
+fminnm {z20.s, z21.s}, {z20.s, z21.s}, {z20.s, z21.s} // 11000001-10110100-10110001-00110101
+// CHECK-INST: fminnm { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }
+// CHECK-ENCODING: [0x35,0xb1,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4b135 <unknown>
+
+fminnm {z22.s, z23.s}, {z22.s, z23.s}, {z8.s, z9.s} // 11000001-10101000-10110001-00110111
+// CHECK-INST: fminnm { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }
+// CHECK-ENCODING: [0x37,0xb1,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8b137 <unknown>
+
+fminnm {z30.s, z31.s}, {z30.s, z31.s}, {z30.s, z31.s} // 11000001-10111110-10110001-00111111
+// CHECK-INST: fminnm { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0x3f,0xb1,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1beb13f <unknown>
+
+
+fminnm {z0.d - z3.d}, {z0.d - z3.d}, z0.d // 11000001-11100000-10101001-00100001
+// CHECK-INST: fminnm { z0.d - z3.d }, { z0.d - z3.d }, z0.d
+// CHECK-ENCODING: [0x21,0xa9,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0a921 <unknown>
+
+fminnm {z20.d - z23.d}, {z20.d - z23.d}, z5.d // 11000001-11100101-10101001-00110101
+// CHECK-INST: fminnm { z20.d - z23.d }, { z20.d - z23.d }, z5.d
+// CHECK-ENCODING: [0x35,0xa9,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5a935 <unknown>
+
+fminnm {z20.d - z23.d}, {z20.d - z23.d}, z8.d // 11000001-11101000-10101001-00110101
+// CHECK-INST: fminnm { z20.d - z23.d }, { z20.d - z23.d }, z8.d
+// CHECK-ENCODING: [0x35,0xa9,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8a935 <unknown>
+
+fminnm {z28.d - z31.d}, {z28.d - z31.d}, z15.d // 11000001-11101111-10101001-00111101
+// CHECK-INST: fminnm { z28.d - z31.d }, { z28.d - z31.d }, z15.d
+// CHECK-ENCODING: [0x3d,0xa9,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efa93d <unknown>
+
+
+fminnm {z0.d - z3.d}, {z0.d - z3.d}, {z0.d - z3.d} // 11000001-11100000-10111001-00100001
+// CHECK-INST: fminnm { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x21,0xb9,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0b921 <unknown>
+
+fminnm {z20.d - z23.d}, {z20.d - z23.d}, {z20.d - z23.d} // 11000001-11110100-10111001-00110101
+// CHECK-INST: fminnm { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x35,0xb9,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4b935 <unknown>
+
+fminnm {z20.d - z23.d}, {z20.d - z23.d}, {z8.d - z11.d} // 11000001-11101000-10111001-00110101
+// CHECK-INST: fminnm { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x35,0xb9,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8b935 <unknown>
+
+fminnm {z28.d - z31.d}, {z28.d - z31.d}, {z28.d - z31.d} // 11000001-11111100-10111001-00111101
+// CHECK-INST: fminnm { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x3d,0xb9,0xfc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fcb93d <unknown>
+
+
+fminnm {z0.h - z3.h}, {z0.h - z3.h}, z0.h // 11000001-01100000-10101001-00100001
+// CHECK-INST: fminnm { z0.h - z3.h }, { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x21,0xa9,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160a921 <unknown>
+
+fminnm {z20.h - z23.h}, {z20.h - z23.h}, z5.h // 11000001-01100101-10101001-00110101
+// CHECK-INST: fminnm { z20.h - z23.h }, { z20.h - z23.h }, z5.h
+// CHECK-ENCODING: [0x35,0xa9,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165a935 <unknown>
+
+fminnm {z20.h - z23.h}, {z20.h - z23.h}, z8.h // 11000001-01101000-10101001-00110101
+// CHECK-INST: fminnm { z20.h - z23.h }, { z20.h - z23.h }, z8.h
+// CHECK-ENCODING: [0x35,0xa9,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168a935 <unknown>
+
+fminnm {z28.h - z31.h}, {z28.h - z31.h}, z15.h // 11000001-01101111-10101001-00111101
+// CHECK-INST: fminnm { z28.h - z31.h }, { z28.h - z31.h }, z15.h
+// CHECK-ENCODING: [0x3d,0xa9,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fa93d <unknown>
+
+
+fminnm {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h} // 11000001-01100000-10111001-00100001
+// CHECK-INST: fminnm { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x21,0xb9,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160b921 <unknown>
+
+fminnm {z20.h - z23.h}, {z20.h - z23.h}, {z20.h - z23.h} // 11000001-01110100-10111001-00110101
+// CHECK-INST: fminnm { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x35,0xb9,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174b935 <unknown>
+
+fminnm {z20.h - z23.h}, {z20.h - z23.h}, {z8.h - z11.h} // 11000001-01101000-10111001-00110101
+// CHECK-INST: fminnm { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x35,0xb9,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168b935 <unknown>
+
+fminnm {z28.h - z31.h}, {z28.h - z31.h}, {z28.h - z31.h} // 11000001-01111100-10111001-00111101
+// CHECK-INST: fminnm { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x3d,0xb9,0x7c,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17cb93d <unknown>
+
+
+fminnm {z0.s - z3.s}, {z0.s - z3.s}, z0.s // 11000001-10100000-10101001-00100001
+// CHECK-INST: fminnm { z0.s - z3.s }, { z0.s - z3.s }, z0.s
+// CHECK-ENCODING: [0x21,0xa9,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0a921 <unknown>
+
+fminnm {z20.s - z23.s}, {z20.s - z23.s}, z5.s // 11000001-10100101-10101001-00110101
+// CHECK-INST: fminnm { z20.s - z23.s }, { z20.s - z23.s }, z5.s
+// CHECK-ENCODING: [0x35,0xa9,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5a935 <unknown>
+
+fminnm {z20.s - z23.s}, {z20.s - z23.s}, z8.s // 11000001-10101000-10101001-00110101
+// CHECK-INST: fminnm { z20.s - z23.s }, { z20.s - z23.s }, z8.s
+// CHECK-ENCODING: [0x35,0xa9,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8a935 <unknown>
+
+fminnm {z28.s - z31.s}, {z28.s - z31.s}, z15.s // 11000001-10101111-10101001-00111101
+// CHECK-INST: fminnm { z28.s - z31.s }, { z28.s - z31.s }, z15.s
+// CHECK-ENCODING: [0x3d,0xa9,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afa93d <unknown>
+
+
+fminnm {z0.s - z3.s}, {z0.s - z3.s}, {z0.s - z3.s} // 11000001-10100000-10111001-00100001
+// CHECK-INST: fminnm { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x21,0xb9,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0b921 <unknown>
+
+fminnm {z20.s - z23.s}, {z20.s - z23.s}, {z20.s - z23.s} // 11000001-10110100-10111001-00110101
+// CHECK-INST: fminnm { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }
+// CHECK-ENCODING: [0x35,0xb9,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4b935 <unknown>
+
+fminnm {z20.s - z23.s}, {z20.s - z23.s}, {z8.s - z11.s} // 11000001-10101000-10111001-00110101
+// CHECK-INST: fminnm { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x35,0xb9,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8b935 <unknown>
+
+fminnm {z28.s - z31.s}, {z28.s - z31.s}, {z28.s - z31.s} // 11000001-10111100-10111001-00111101
+// CHECK-INST: fminnm { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x3d,0xb9,0xbc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bcb93d <unknown>
+
diff --git a/llvm/test/MC/AArch64/SME2/smax-diagnostics.s b/llvm/test/MC/AArch64/SME2/smax-diagnostics.s
new file mode 100644
index 0000000000000..0411688fb978d
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/smax-diagnostics.s
@@ -0,0 +1,30 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+smax {z0.h, z1.h}, {z0.h-z2.h}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: smax {z0.h, z1.h}, {z0.h-z2.h}, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smax {z1.d-z2.d}, {z0.d, z1.d}, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element type
+// CHECK-NEXT: smax {z1.d-z2.d}, {z0.d, z1.d}, z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid single register
+
+smax {z0.b, z1.b}, {z2.b-z3.b}, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
+// CHECK-NEXT: smax {z0.b, z1.b}, {z2.b-z3.b}, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+smax {z0.b, z1.b}, {z2.b-z3.b}, z14.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
+// CHECK-NEXT: smax {z0.b, z1.b}, {z2.b-z3.b}, z14.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2/smax.s b/llvm/test/MC/AArch64/SME2/smax.s
new file mode 100644
index 0000000000000..b9ca956a9508f
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/smax.s
@@ -0,0 +1,413 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+smax {z0.h, z1.h}, {z0.h, z1.h}, z0.h // 11000001-01100000-10100000-00000000
+// CHECK-INST: smax { z0.h, z1.h }, { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x00,0xa0,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160a000 <unknown>
+
+smax {z20.h, z21.h}, {z20.h, z21.h}, z5.h // 11000001-01100101-10100000-00010100
+// CHECK-INST: smax { z20.h, z21.h }, { z20.h, z21.h }, z5.h
+// CHECK-ENCODING: [0x14,0xa0,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165a014 <unknown>
+
+smax {z22.h, z23.h}, {z22.h, z23.h}, z8.h // 11000001-01101000-10100000-00010110
+// CHECK-INST: smax { z22.h, z23.h }, { z22.h, z23.h }, z8.h
+// CHECK-ENCODING: [0x16,0xa0,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168a016 <unknown>
+
+smax {z30.h, z31.h}, {z30.h, z31.h}, z15.h // 11000001-01101111-10100000-00011110
+// CHECK-INST: smax { z30.h, z31.h }, { z30.h, z31.h }, z15.h
+// CHECK-ENCODING: [0x1e,0xa0,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fa01e <unknown>
+
+
+smax {z0.h, z1.h}, {z0.h, z1.h}, {z0.h, z1.h} // 11000001-01100000-10110000-00000000
+// CHECK-INST: smax { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x00,0xb0,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160b000 <unknown>
+
+smax {z20.h, z21.h}, {z20.h, z21.h}, {z20.h, z21.h} // 11000001-01110100-10110000-00010100
+// CHECK-INST: smax { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x14,0xb0,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174b014 <unknown>
+
+smax {z22.h, z23.h}, {z22.h, z23.h}, {z8.h, z9.h} // 11000001-01101000-10110000-00010110
+// CHECK-INST: smax { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }
+// CHECK-ENCODING: [0x16,0xb0,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168b016 <unknown>
+
+smax {z30.h, z31.h}, {z30.h, z31.h}, {z30.h, z31.h} // 11000001-01111110-10110000-00011110
+// CHECK-INST: smax { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0x1e,0xb0,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17eb01e <unknown>
+
+
+smax {z0.s, z1.s}, {z0.s, z1.s}, z0.s // 11000001-10100000-10100000-00000000
+// CHECK-INST: smax { z0.s, z1.s }, { z0.s, z1.s }, z0.s
+// CHECK-ENCODING: [0x00,0xa0,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0a000 <unknown>
+
+smax {z20.s, z21.s}, {z20.s, z21.s}, z5.s // 11000001-10100101-10100000-00010100
+// CHECK-INST: smax { z20.s, z21.s }, { z20.s, z21.s }, z5.s
+// CHECK-ENCODING: [0x14,0xa0,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5a014 <unknown>
+
+smax {z22.s, z23.s}, {z22.s, z23.s}, z8.s // 11000001-10101000-10100000-00010110
+// CHECK-INST: smax { z22.s, z23.s }, { z22.s, z23.s }, z8.s
+// CHECK-ENCODING: [0x16,0xa0,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8a016 <unknown>
+
+smax {z30.s, z31.s}, {z30.s, z31.s}, z15.s // 11000001-10101111-10100000-00011110
+// CHECK-INST: smax { z30.s, z31.s }, { z30.s, z31.s }, z15.s
+// CHECK-ENCODING: [0x1e,0xa0,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afa01e <unknown>
+
+
+smax {z0.s, z1.s}, {z0.s, z1.s}, {z0.s, z1.s} // 11000001-10100000-10110000-00000000
+// CHECK-INST: smax { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x00,0xb0,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0b000 <unknown>
+
+smax {z20.s, z21.s}, {z20.s, z21.s}, {z20.s, z21.s} // 11000001-10110100-10110000-00010100
+// CHECK-INST: smax { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }
+// CHECK-ENCODING: [0x14,0xb0,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4b014 <unknown>
+
+smax {z22.s, z23.s}, {z22.s, z23.s}, {z8.s, z9.s} // 11000001-10101000-10110000-00010110
+// CHECK-INST: smax { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }
+// CHECK-ENCODING: [0x16,0xb0,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8b016 <unknown>
+
+smax {z30.s, z31.s}, {z30.s, z31.s}, {z30.s, z31.s} // 11000001-10111110-10110000-00011110
+// CHECK-INST: smax { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0x1e,0xb0,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1beb01e <unknown>
+
+
+smax {z0.d, z1.d}, {z0.d, z1.d}, z0.d // 11000001-11100000-10100000-00000000
+// CHECK-INST: smax { z0.d, z1.d }, { z0.d, z1.d }, z0.d
+// CHECK-ENCODING: [0x00,0xa0,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0a000 <unknown>
+
+smax {z20.d, z21.d}, {z20.d, z21.d}, z5.d // 11000001-11100101-10100000-00010100
+// CHECK-INST: smax { z20.d, z21.d }, { z20.d, z21.d }, z5.d
+// CHECK-ENCODING: [0x14,0xa0,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5a014 <unknown>
+
+smax {z22.d, z23.d}, {z22.d, z23.d}, z8.d // 11000001-11101000-10100000-00010110
+// CHECK-INST: smax { z22.d, z23.d }, { z22.d, z23.d }, z8.d
+// CHECK-ENCODING: [0x16,0xa0,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8a016 <unknown>
+
+smax {z30.d, z31.d}, {z30.d, z31.d}, z15.d // 11000001-11101111-10100000-00011110
+// CHECK-INST: smax { z30.d, z31.d }, { z30.d, z31.d }, z15.d
+// CHECK-ENCODING: [0x1e,0xa0,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efa01e <unknown>
+
+
+smax {z0.d, z1.d}, {z0.d, z1.d}, {z0.d, z1.d} // 11000001-11100000-10110000-00000000
+// CHECK-INST: smax { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }
+// CHECK-ENCODING: [0x00,0xb0,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0b000 <unknown>
+
+smax {z20.d, z21.d}, {z20.d, z21.d}, {z20.d, z21.d} // 11000001-11110100-10110000-00010100
+// CHECK-INST: smax { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }
+// CHECK-ENCODING: [0x14,0xb0,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4b014 <unknown>
+
+smax {z22.d, z23.d}, {z22.d, z23.d}, {z8.d, z9.d} // 11000001-11101000-10110000-00010110
+// CHECK-INST: smax { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }
+// CHECK-ENCODING: [0x16,0xb0,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8b016 <unknown>
+
+smax {z30.d, z31.d}, {z30.d, z31.d}, {z30.d, z31.d} // 11000001-11111110-10110000-00011110
+// CHECK-INST: smax { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0x1e,0xb0,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1feb01e <unknown>
+
+
+smax {z0.b, z1.b}, {z0.b, z1.b}, z0.b // 11000001-00100000-10100000-00000000
+// CHECK-INST: smax { z0.b, z1.b }, { z0.b, z1.b }, z0.b
+// CHECK-ENCODING: [0x00,0xa0,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120a000 <unknown>
+
+smax {z20.b, z21.b}, {z20.b, z21.b}, z5.b // 11000001-00100101-10100000-00010100
+// CHECK-INST: smax { z20.b, z21.b }, { z20.b, z21.b }, z5.b
+// CHECK-ENCODING: [0x14,0xa0,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c125a014 <unknown>
+
+smax {z22.b, z23.b}, {z22.b, z23.b}, z8.b // 11000001-00101000-10100000-00010110
+// CHECK-INST: smax { z22.b, z23.b }, { z22.b, z23.b }, z8.b
+// CHECK-ENCODING: [0x16,0xa0,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128a016 <unknown>
+
+smax {z30.b, z31.b}, {z30.b, z31.b}, z15.b // 11000001-00101111-10100000-00011110
+// CHECK-INST: smax { z30.b, z31.b }, { z30.b, z31.b }, z15.b
+// CHECK-ENCODING: [0x1e,0xa0,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12fa01e <unknown>
+
+
+smax {z0.b, z1.b}, {z0.b, z1.b}, {z0.b, z1.b} // 11000001-00100000-10110000-00000000
+// CHECK-INST: smax { z0.b, z1.b }, { z0.b, z1.b }, { z0.b, z1.b }
+// CHECK-ENCODING: [0x00,0xb0,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120b000 <unknown>
+
+smax {z20.b, z21.b}, {z20.b, z21.b}, {z20.b, z21.b} // 11000001-00110100-10110000-00010100
+// CHECK-INST: smax { z20.b, z21.b }, { z20.b, z21.b }, { z20.b, z21.b }
+// CHECK-ENCODING: [0x14,0xb0,0x34,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c134b014 <unknown>
+
+smax {z22.b, z23.b}, {z22.b, z23.b}, {z8.b, z9.b} // 11000001-00101000-10110000-00010110
+// CHECK-INST: smax { z22.b, z23.b }, { z22.b, z23.b }, { z8.b, z9.b }
+// CHECK-ENCODING: [0x16,0xb0,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128b016 <unknown>
+
+smax {z30.b, z31.b}, {z30.b, z31.b}, {z30.b, z31.b} // 11000001-00111110-10110000-00011110
+// CHECK-INST: smax { z30.b, z31.b }, { z30.b, z31.b }, { z30.b, z31.b }
+// CHECK-ENCODING: [0x1e,0xb0,0x3e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13eb01e <unknown>
+
+
+smax {z0.h - z3.h}, {z0.h - z3.h}, z0.h // 11000001-01100000-10101000-00000000
+// CHECK-INST: smax { z0.h - z3.h }, { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x00,0xa8,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160a800 <unknown>
+
+smax {z20.h - z23.h}, {z20.h - z23.h}, z5.h // 11000001-01100101-10101000-00010100
+// CHECK-INST: smax { z20.h - z23.h }, { z20.h - z23.h }, z5.h
+// CHECK-ENCODING: [0x14,0xa8,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165a814 <unknown>
+
+smax {z20.h - z23.h}, {z20.h - z23.h}, z8.h // 11000001-01101000-10101000-00010100
+// CHECK-INST: smax { z20.h - z23.h }, { z20.h - z23.h }, z8.h
+// CHECK-ENCODING: [0x14,0xa8,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168a814 <unknown>
+
+smax {z28.h - z31.h}, {z28.h - z31.h}, z15.h // 11000001-01101111-10101000-00011100
+// CHECK-INST: smax { z28.h - z31.h }, { z28.h - z31.h }, z15.h
+// CHECK-ENCODING: [0x1c,0xa8,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fa81c <unknown>
+
+
+smax {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h} // 11000001-01100000-10111000-00000000
+// CHECK-INST: smax { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x00,0xb8,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160b800 <unknown>
+
+smax {z20.h - z23.h}, {z20.h - z23.h}, {z20.h - z23.h} // 11000001-01110100-10111000-00010100
+// CHECK-INST: smax { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x14,0xb8,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174b814 <unknown>
+
+smax {z20.h - z23.h}, {z20.h - z23.h}, {z8.h - z11.h} // 11000001-01101000-10111000-00010100
+// CHECK-INST: smax { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x14,0xb8,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168b814 <unknown>
+
+smax {z28.h - z31.h}, {z28.h - z31.h}, {z28.h - z31.h} // 11000001-01111100-10111000-00011100
+// CHECK-INST: smax { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x1c,0xb8,0x7c,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17cb81c <unknown>
+
+
+smax {z0.s - z3.s}, {z0.s - z3.s}, z0.s // 11000001-10100000-10101000-00000000
+// CHECK-INST: smax { z0.s - z3.s }, { z0.s - z3.s }, z0.s
+// CHECK-ENCODING: [0x00,0xa8,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0a800 <unknown>
+
+smax {z20.s - z23.s}, {z20.s - z23.s}, z5.s // 11000001-10100101-10101000-00010100
+// CHECK-INST: smax { z20.s - z23.s }, { z20.s - z23.s }, z5.s
+// CHECK-ENCODING: [0x14,0xa8,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5a814 <unknown>
+
+smax {z20.s - z23.s}, {z20.s - z23.s}, z8.s // 11000001-10101000-10101000-00010100
+// CHECK-INST: smax { z20.s - z23.s }, { z20.s - z23.s }, z8.s
+// CHECK-ENCODING: [0x14,0xa8,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8a814 <unknown>
+
+smax {z28.s - z31.s}, {z28.s - z31.s}, z15.s // 11000001-10101111-10101000-00011100
+// CHECK-INST: smax { z28.s - z31.s }, { z28.s - z31.s }, z15.s
+// CHECK-ENCODING: [0x1c,0xa8,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afa81c <unknown>
+
+
+smax {z0.s - z3.s}, {z0.s - z3.s}, {z0.s - z3.s} // 11000001-10100000-10111000-00000000
+// CHECK-INST: smax { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x00,0xb8,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0b800 <unknown>
+
+smax {z20.s - z23.s}, {z20.s - z23.s}, {z20.s - z23.s} // 11000001-10110100-10111000-00010100
+// CHECK-INST: smax { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }
+// CHECK-ENCODING: [0x14,0xb8,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4b814 <unknown>
+
+smax {z20.s - z23.s}, {z20.s - z23.s}, {z8.s - z11.s} // 11000001-10101000-10111000-00010100
+// CHECK-INST: smax { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x14,0xb8,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8b814 <unknown>
+
+smax {z28.s - z31.s}, {z28.s - z31.s}, {z28.s - z31.s} // 11000001-10111100-10111000-00011100
+// CHECK-INST: smax { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x1c,0xb8,0xbc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bcb81c <unknown>
+
+
+smax {z0.d - z3.d}, {z0.d - z3.d}, z0.d // 11000001-11100000-10101000-00000000
+// CHECK-INST: smax { z0.d - z3.d }, { z0.d - z3.d }, z0.d
+// CHECK-ENCODING: [0x00,0xa8,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0a800 <unknown>
+
+smax {z20.d - z23.d}, {z20.d - z23.d}, z5.d // 11000001-11100101-10101000-00010100
+// CHECK-INST: smax { z20.d - z23.d }, { z20.d - z23.d }, z5.d
+// CHECK-ENCODING: [0x14,0xa8,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5a814 <unknown>
+
+smax {z20.d - z23.d}, {z20.d - z23.d}, z8.d // 11000001-11101000-10101000-00010100
+// CHECK-INST: smax { z20.d - z23.d }, { z20.d - z23.d }, z8.d
+// CHECK-ENCODING: [0x14,0xa8,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8a814 <unknown>
+
+smax {z28.d - z31.d}, {z28.d - z31.d}, z15.d // 11000001-11101111-10101000-00011100
+// CHECK-INST: smax { z28.d - z31.d }, { z28.d - z31.d }, z15.d
+// CHECK-ENCODING: [0x1c,0xa8,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efa81c <unknown>
+
+
+smax {z0.d - z3.d}, {z0.d - z3.d}, {z0.d - z3.d} // 11000001-11100000-10111000-00000000
+// CHECK-INST: smax { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x00,0xb8,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0b800 <unknown>
+
+smax {z20.d - z23.d}, {z20.d - z23.d}, {z20.d - z23.d} // 11000001-11110100-10111000-00010100
+// CHECK-INST: smax { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x14,0xb8,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4b814 <unknown>
+
+smax {z20.d - z23.d}, {z20.d - z23.d}, {z8.d - z11.d} // 11000001-11101000-10111000-00010100
+// CHECK-INST: smax { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x14,0xb8,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8b814 <unknown>
+
+smax {z28.d - z31.d}, {z28.d - z31.d}, {z28.d - z31.d} // 11000001-11111100-10111000-00011100
+// CHECK-INST: smax { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x1c,0xb8,0xfc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fcb81c <unknown>
+
+
+smax {z0.b - z3.b}, {z0.b - z3.b}, z0.b // 11000001-00100000-10101000-00000000
+// CHECK-INST: smax { z0.b - z3.b }, { z0.b - z3.b }, z0.b
+// CHECK-ENCODING: [0x00,0xa8,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120a800 <unknown>
+
+smax {z20.b - z23.b}, {z20.b - z23.b}, z5.b // 11000001-00100101-10101000-00010100
+// CHECK-INST: smax { z20.b - z23.b }, { z20.b - z23.b }, z5.b
+// CHECK-ENCODING: [0x14,0xa8,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c125a814 <unknown>
+
+smax {z20.b - z23.b}, {z20.b - z23.b}, z8.b // 11000001-00101000-10101000-00010100
+// CHECK-INST: smax { z20.b - z23.b }, { z20.b - z23.b }, z8.b
+// CHECK-ENCODING: [0x14,0xa8,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128a814 <unknown>
+
+smax {z28.b - z31.b}, {z28.b - z31.b}, z15.b // 11000001-00101111-10101000-00011100
+// CHECK-INST: smax { z28.b - z31.b }, { z28.b - z31.b }, z15.b
+// CHECK-ENCODING: [0x1c,0xa8,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12fa81c <unknown>
+
+
+smax {z0.b - z3.b}, {z0.b - z3.b}, {z0.b - z3.b} // 11000001-00100000-10111000-00000000
+// CHECK-INST: smax { z0.b - z3.b }, { z0.b - z3.b }, { z0.b - z3.b }
+// CHECK-ENCODING: [0x00,0xb8,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120b800 <unknown>
+
+smax {z20.b - z23.b}, {z20.b - z23.b}, {z20.b - z23.b} // 11000001-00110100-10111000-00010100
+// CHECK-INST: smax { z20.b - z23.b }, { z20.b - z23.b }, { z20.b - z23.b }
+// CHECK-ENCODING: [0x14,0xb8,0x34,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c134b814 <unknown>
+
+smax {z20.b - z23.b}, {z20.b - z23.b}, {z8.b - z11.b} // 11000001-00101000-10111000-00010100
+// CHECK-INST: smax { z20.b - z23.b }, { z20.b - z23.b }, { z8.b - z11.b }
+// CHECK-ENCODING: [0x14,0xb8,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128b814 <unknown>
+
+smax {z28.b - z31.b}, {z28.b - z31.b}, {z28.b - z31.b} // 11000001-00111100-10111000-00011100
+// CHECK-INST: smax { z28.b - z31.b }, { z28.b - z31.b }, { z28.b - z31.b }
+// CHECK-ENCODING: [0x1c,0xb8,0x3c,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13cb81c <unknown>
+
diff --git a/llvm/test/MC/AArch64/SME2/smin-diagnostics.s b/llvm/test/MC/AArch64/SME2/smin-diagnostics.s
new file mode 100644
index 0000000000000..ac6fb5d67dbc5
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/smin-diagnostics.s
@@ -0,0 +1,30 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+smin {z0.h, z1.h}, {z0.h-z2.h}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: smin {z0.h, z1.h}, {z0.h-z2.h}, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smin {z1.d-z2.d}, {z0.d, z1.d}, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element type
+// CHECK-NEXT: smin {z1.d-z2.d}, {z0.d, z1.d}, z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid single register
+
+smin {z0.b, z1.b}, {z2.b-z3.b}, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
+// CHECK-NEXT: smin {z0.b, z1.b}, {z2.b-z3.b}, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+smin {z0.b, z1.b}, {z2.b-z3.b}, z14.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
+// CHECK-NEXT: smin {z0.b, z1.b}, {z2.b-z3.b}, z14.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2/smin.s b/llvm/test/MC/AArch64/SME2/smin.s
new file mode 100644
index 0000000000000..6f83d8bcfffe9
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/smin.s
@@ -0,0 +1,413 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+smin {z0.h, z1.h}, {z0.h, z1.h}, z0.h // 11000001-01100000-10100000-00100000
+// CHECK-INST: smin { z0.h, z1.h }, { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x20,0xa0,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160a020 <unknown>
+
+smin {z20.h, z21.h}, {z20.h, z21.h}, z5.h // 11000001-01100101-10100000-00110100
+// CHECK-INST: smin { z20.h, z21.h }, { z20.h, z21.h }, z5.h
+// CHECK-ENCODING: [0x34,0xa0,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165a034 <unknown>
+
+smin {z22.h, z23.h}, {z22.h, z23.h}, z8.h // 11000001-01101000-10100000-00110110
+// CHECK-INST: smin { z22.h, z23.h }, { z22.h, z23.h }, z8.h
+// CHECK-ENCODING: [0x36,0xa0,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168a036 <unknown>
+
+smin {z30.h, z31.h}, {z30.h, z31.h}, z15.h // 11000001-01101111-10100000-00111110
+// CHECK-INST: smin { z30.h, z31.h }, { z30.h, z31.h }, z15.h
+// CHECK-ENCODING: [0x3e,0xa0,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fa03e <unknown>
+
+
+smin {z0.h, z1.h}, {z0.h, z1.h}, {z0.h, z1.h} // 11000001-01100000-10110000-00100000
+// CHECK-INST: smin { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x20,0xb0,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160b020 <unknown>
+
+smin {z20.h, z21.h}, {z20.h, z21.h}, {z20.h, z21.h} // 11000001-01110100-10110000-00110100
+// CHECK-INST: smin { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x34,0xb0,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174b034 <unknown>
+
+smin {z22.h, z23.h}, {z22.h, z23.h}, {z8.h, z9.h} // 11000001-01101000-10110000-00110110
+// CHECK-INST: smin { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }
+// CHECK-ENCODING: [0x36,0xb0,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168b036 <unknown>
+
+smin {z30.h, z31.h}, {z30.h, z31.h}, {z30.h, z31.h} // 11000001-01111110-10110000-00111110
+// CHECK-INST: smin { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0x3e,0xb0,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17eb03e <unknown>
+
+
+smin {z0.s, z1.s}, {z0.s, z1.s}, z0.s // 11000001-10100000-10100000-00100000
+// CHECK-INST: smin { z0.s, z1.s }, { z0.s, z1.s }, z0.s
+// CHECK-ENCODING: [0x20,0xa0,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0a020 <unknown>
+
+smin {z20.s, z21.s}, {z20.s, z21.s}, z5.s // 11000001-10100101-10100000-00110100
+// CHECK-INST: smin { z20.s, z21.s }, { z20.s, z21.s }, z5.s
+// CHECK-ENCODING: [0x34,0xa0,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5a034 <unknown>
+
+smin {z22.s, z23.s}, {z22.s, z23.s}, z8.s // 11000001-10101000-10100000-00110110
+// CHECK-INST: smin { z22.s, z23.s }, { z22.s, z23.s }, z8.s
+// CHECK-ENCODING: [0x36,0xa0,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8a036 <unknown>
+
+smin {z30.s, z31.s}, {z30.s, z31.s}, z15.s // 11000001-10101111-10100000-00111110
+// CHECK-INST: smin { z30.s, z31.s }, { z30.s, z31.s }, z15.s
+// CHECK-ENCODING: [0x3e,0xa0,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afa03e <unknown>
+
+
+smin {z0.s, z1.s}, {z0.s, z1.s}, {z0.s, z1.s} // 11000001-10100000-10110000-00100000
+// CHECK-INST: smin { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x20,0xb0,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0b020 <unknown>
+
+smin {z20.s, z21.s}, {z20.s, z21.s}, {z20.s, z21.s} // 11000001-10110100-10110000-00110100
+// CHECK-INST: smin { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }
+// CHECK-ENCODING: [0x34,0xb0,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4b034 <unknown>
+
+smin {z22.s, z23.s}, {z22.s, z23.s}, {z8.s, z9.s} // 11000001-10101000-10110000-00110110
+// CHECK-INST: smin { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }
+// CHECK-ENCODING: [0x36,0xb0,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8b036 <unknown>
+
+smin {z30.s, z31.s}, {z30.s, z31.s}, {z30.s, z31.s} // 11000001-10111110-10110000-00111110
+// CHECK-INST: smin { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0x3e,0xb0,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1beb03e <unknown>
+
+
+smin {z0.d, z1.d}, {z0.d, z1.d}, z0.d // 11000001-11100000-10100000-00100000
+// CHECK-INST: smin { z0.d, z1.d }, { z0.d, z1.d }, z0.d
+// CHECK-ENCODING: [0x20,0xa0,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0a020 <unknown>
+
+smin {z20.d, z21.d}, {z20.d, z21.d}, z5.d // 11000001-11100101-10100000-00110100
+// CHECK-INST: smin { z20.d, z21.d }, { z20.d, z21.d }, z5.d
+// CHECK-ENCODING: [0x34,0xa0,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5a034 <unknown>
+
+smin {z22.d, z23.d}, {z22.d, z23.d}, z8.d // 11000001-11101000-10100000-00110110
+// CHECK-INST: smin { z22.d, z23.d }, { z22.d, z23.d }, z8.d
+// CHECK-ENCODING: [0x36,0xa0,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8a036 <unknown>
+
+smin {z30.d, z31.d}, {z30.d, z31.d}, z15.d // 11000001-11101111-10100000-00111110
+// CHECK-INST: smin { z30.d, z31.d }, { z30.d, z31.d }, z15.d
+// CHECK-ENCODING: [0x3e,0xa0,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efa03e <unknown>
+
+
+smin {z0.d, z1.d}, {z0.d, z1.d}, {z0.d, z1.d} // 11000001-11100000-10110000-00100000
+// CHECK-INST: smin { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }
+// CHECK-ENCODING: [0x20,0xb0,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0b020 <unknown>
+
+smin {z20.d, z21.d}, {z20.d, z21.d}, {z20.d, z21.d} // 11000001-11110100-10110000-00110100
+// CHECK-INST: smin { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }
+// CHECK-ENCODING: [0x34,0xb0,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4b034 <unknown>
+
+smin {z22.d, z23.d}, {z22.d, z23.d}, {z8.d, z9.d} // 11000001-11101000-10110000-00110110
+// CHECK-INST: smin { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }
+// CHECK-ENCODING: [0x36,0xb0,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8b036 <unknown>
+
+smin {z30.d, z31.d}, {z30.d, z31.d}, {z30.d, z31.d} // 11000001-11111110-10110000-00111110
+// CHECK-INST: smin { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0x3e,0xb0,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1feb03e <unknown>
+
+
+smin {z0.b, z1.b}, {z0.b, z1.b}, z0.b // 11000001-00100000-10100000-00100000
+// CHECK-INST: smin { z0.b, z1.b }, { z0.b, z1.b }, z0.b
+// CHECK-ENCODING: [0x20,0xa0,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120a020 <unknown>
+
+smin {z20.b, z21.b}, {z20.b, z21.b}, z5.b // 11000001-00100101-10100000-00110100
+// CHECK-INST: smin { z20.b, z21.b }, { z20.b, z21.b }, z5.b
+// CHECK-ENCODING: [0x34,0xa0,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c125a034 <unknown>
+
+smin {z22.b, z23.b}, {z22.b, z23.b}, z8.b // 11000001-00101000-10100000-00110110
+// CHECK-INST: smin { z22.b, z23.b }, { z22.b, z23.b }, z8.b
+// CHECK-ENCODING: [0x36,0xa0,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128a036 <unknown>
+
+smin {z30.b, z31.b}, {z30.b, z31.b}, z15.b // 11000001-00101111-10100000-00111110
+// CHECK-INST: smin { z30.b, z31.b }, { z30.b, z31.b }, z15.b
+// CHECK-ENCODING: [0x3e,0xa0,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12fa03e <unknown>
+
+
+smin {z0.b, z1.b}, {z0.b, z1.b}, {z0.b, z1.b} // 11000001-00100000-10110000-00100000
+// CHECK-INST: smin { z0.b, z1.b }, { z0.b, z1.b }, { z0.b, z1.b }
+// CHECK-ENCODING: [0x20,0xb0,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120b020 <unknown>
+
+smin {z20.b, z21.b}, {z20.b, z21.b}, {z20.b, z21.b} // 11000001-00110100-10110000-00110100
+// CHECK-INST: smin { z20.b, z21.b }, { z20.b, z21.b }, { z20.b, z21.b }
+// CHECK-ENCODING: [0x34,0xb0,0x34,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c134b034 <unknown>
+
+smin {z22.b, z23.b}, {z22.b, z23.b}, {z8.b, z9.b} // 11000001-00101000-10110000-00110110
+// CHECK-INST: smin { z22.b, z23.b }, { z22.b, z23.b }, { z8.b, z9.b }
+// CHECK-ENCODING: [0x36,0xb0,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128b036 <unknown>
+
+smin {z30.b, z31.b}, {z30.b, z31.b}, {z30.b, z31.b} // 11000001-00111110-10110000-00111110
+// CHECK-INST: smin { z30.b, z31.b }, { z30.b, z31.b }, { z30.b, z31.b }
+// CHECK-ENCODING: [0x3e,0xb0,0x3e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13eb03e <unknown>
+
+
+smin {z0.h - z3.h}, {z0.h - z3.h}, z0.h // 11000001-01100000-10101000-00100000
+// CHECK-INST: smin { z0.h - z3.h }, { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x20,0xa8,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160a820 <unknown>
+
+smin {z20.h - z23.h}, {z20.h - z23.h}, z5.h // 11000001-01100101-10101000-00110100
+// CHECK-INST: smin { z20.h - z23.h }, { z20.h - z23.h }, z5.h
+// CHECK-ENCODING: [0x34,0xa8,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165a834 <unknown>
+
+smin {z20.h - z23.h}, {z20.h - z23.h}, z8.h // 11000001-01101000-10101000-00110100
+// CHECK-INST: smin { z20.h - z23.h }, { z20.h - z23.h }, z8.h
+// CHECK-ENCODING: [0x34,0xa8,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168a834 <unknown>
+
+smin {z28.h - z31.h}, {z28.h - z31.h}, z15.h // 11000001-01101111-10101000-00111100
+// CHECK-INST: smin { z28.h - z31.h }, { z28.h - z31.h }, z15.h
+// CHECK-ENCODING: [0x3c,0xa8,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fa83c <unknown>
+
+
+smin {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h} // 11000001-01100000-10111000-00100000
+// CHECK-INST: smin { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x20,0xb8,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160b820 <unknown>
+
+smin {z20.h - z23.h}, {z20.h - z23.h}, {z20.h - z23.h} // 11000001-01110100-10111000-00110100
+// CHECK-INST: smin { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x34,0xb8,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174b834 <unknown>
+
+smin {z20.h - z23.h}, {z20.h - z23.h}, {z8.h - z11.h} // 11000001-01101000-10111000-00110100
+// CHECK-INST: smin { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x34,0xb8,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168b834 <unknown>
+
+smin {z28.h - z31.h}, {z28.h - z31.h}, {z28.h - z31.h} // 11000001-01111100-10111000-00111100
+// CHECK-INST: smin { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x3c,0xb8,0x7c,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17cb83c <unknown>
+
+
+smin {z0.s - z3.s}, {z0.s - z3.s}, z0.s // 11000001-10100000-10101000-00100000
+// CHECK-INST: smin { z0.s - z3.s }, { z0.s - z3.s }, z0.s
+// CHECK-ENCODING: [0x20,0xa8,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0a820 <unknown>
+
+smin {z20.s - z23.s}, {z20.s - z23.s}, z5.s // 11000001-10100101-10101000-00110100
+// CHECK-INST: smin { z20.s - z23.s }, { z20.s - z23.s }, z5.s
+// CHECK-ENCODING: [0x34,0xa8,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5a834 <unknown>
+
+smin {z20.s - z23.s}, {z20.s - z23.s}, z8.s // 11000001-10101000-10101000-00110100
+// CHECK-INST: smin { z20.s - z23.s }, { z20.s - z23.s }, z8.s
+// CHECK-ENCODING: [0x34,0xa8,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8a834 <unknown>
+
+smin {z28.s - z31.s}, {z28.s - z31.s}, z15.s // 11000001-10101111-10101000-00111100
+// CHECK-INST: smin { z28.s - z31.s }, { z28.s - z31.s }, z15.s
+// CHECK-ENCODING: [0x3c,0xa8,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afa83c <unknown>
+
+
+smin {z0.s - z3.s}, {z0.s - z3.s}, {z0.s - z3.s} // 11000001-10100000-10111000-00100000
+// CHECK-INST: smin { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x20,0xb8,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0b820 <unknown>
+
+smin {z20.s - z23.s}, {z20.s - z23.s}, {z20.s - z23.s} // 11000001-10110100-10111000-00110100
+// CHECK-INST: smin { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }
+// CHECK-ENCODING: [0x34,0xb8,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4b834 <unknown>
+
+smin {z20.s - z23.s}, {z20.s - z23.s}, {z8.s - z11.s} // 11000001-10101000-10111000-00110100
+// CHECK-INST: smin { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x34,0xb8,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8b834 <unknown>
+
+smin {z28.s - z31.s}, {z28.s - z31.s}, {z28.s - z31.s} // 11000001-10111100-10111000-00111100
+// CHECK-INST: smin { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x3c,0xb8,0xbc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bcb83c <unknown>
+
+
+smin {z0.d - z3.d}, {z0.d - z3.d}, z0.d // 11000001-11100000-10101000-00100000
+// CHECK-INST: smin { z0.d - z3.d }, { z0.d - z3.d }, z0.d
+// CHECK-ENCODING: [0x20,0xa8,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0a820 <unknown>
+
+smin {z20.d - z23.d}, {z20.d - z23.d}, z5.d // 11000001-11100101-10101000-00110100
+// CHECK-INST: smin { z20.d - z23.d }, { z20.d - z23.d }, z5.d
+// CHECK-ENCODING: [0x34,0xa8,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5a834 <unknown>
+
+smin {z20.d - z23.d}, {z20.d - z23.d}, z8.d // 11000001-11101000-10101000-00110100
+// CHECK-INST: smin { z20.d - z23.d }, { z20.d - z23.d }, z8.d
+// CHECK-ENCODING: [0x34,0xa8,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8a834 <unknown>
+
+smin {z28.d - z31.d}, {z28.d - z31.d}, z15.d // 11000001-11101111-10101000-00111100
+// CHECK-INST: smin { z28.d - z31.d }, { z28.d - z31.d }, z15.d
+// CHECK-ENCODING: [0x3c,0xa8,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efa83c <unknown>
+
+
+smin {z0.d - z3.d}, {z0.d - z3.d}, {z0.d - z3.d} // 11000001-11100000-10111000-00100000
+// CHECK-INST: smin { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x20,0xb8,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0b820 <unknown>
+
+smin {z20.d - z23.d}, {z20.d - z23.d}, {z20.d - z23.d} // 11000001-11110100-10111000-00110100
+// CHECK-INST: smin { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x34,0xb8,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4b834 <unknown>
+
+smin {z20.d - z23.d}, {z20.d - z23.d}, {z8.d - z11.d} // 11000001-11101000-10111000-00110100
+// CHECK-INST: smin { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x34,0xb8,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8b834 <unknown>
+
+smin {z28.d - z31.d}, {z28.d - z31.d}, {z28.d - z31.d} // 11000001-11111100-10111000-00111100
+// CHECK-INST: smin { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x3c,0xb8,0xfc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fcb83c <unknown>
+
+
+smin {z0.b - z3.b}, {z0.b - z3.b}, z0.b // 11000001-00100000-10101000-00100000
+// CHECK-INST: smin { z0.b - z3.b }, { z0.b - z3.b }, z0.b
+// CHECK-ENCODING: [0x20,0xa8,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120a820 <unknown>
+
+smin {z20.b - z23.b}, {z20.b - z23.b}, z5.b // 11000001-00100101-10101000-00110100
+// CHECK-INST: smin { z20.b - z23.b }, { z20.b - z23.b }, z5.b
+// CHECK-ENCODING: [0x34,0xa8,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c125a834 <unknown>
+
+smin {z20.b - z23.b}, {z20.b - z23.b}, z8.b // 11000001-00101000-10101000-00110100
+// CHECK-INST: smin { z20.b - z23.b }, { z20.b - z23.b }, z8.b
+// CHECK-ENCODING: [0x34,0xa8,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128a834 <unknown>
+
+smin {z28.b - z31.b}, {z28.b - z31.b}, z15.b // 11000001-00101111-10101000-00111100
+// CHECK-INST: smin { z28.b - z31.b }, { z28.b - z31.b }, z15.b
+// CHECK-ENCODING: [0x3c,0xa8,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12fa83c <unknown>
+
+
+smin {z0.b - z3.b}, {z0.b - z3.b}, {z0.b - z3.b} // 11000001-00100000-10111000-00100000
+// CHECK-INST: smin { z0.b - z3.b }, { z0.b - z3.b }, { z0.b - z3.b }
+// CHECK-ENCODING: [0x20,0xb8,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120b820 <unknown>
+
+smin {z20.b - z23.b}, {z20.b - z23.b}, {z20.b - z23.b} // 11000001-00110100-10111000-00110100
+// CHECK-INST: smin { z20.b - z23.b }, { z20.b - z23.b }, { z20.b - z23.b }
+// CHECK-ENCODING: [0x34,0xb8,0x34,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c134b834 <unknown>
+
+smin {z20.b - z23.b}, {z20.b - z23.b}, {z8.b - z11.b} // 11000001-00101000-10111000-00110100
+// CHECK-INST: smin { z20.b - z23.b }, { z20.b - z23.b }, { z8.b - z11.b }
+// CHECK-ENCODING: [0x34,0xb8,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128b834 <unknown>
+
+smin {z28.b - z31.b}, {z28.b - z31.b}, {z28.b - z31.b} // 11000001-00111100-10111000-00111100
+// CHECK-INST: smin { z28.b - z31.b }, { z28.b - z31.b }, { z28.b - z31.b }
+// CHECK-ENCODING: [0x3c,0xb8,0x3c,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13cb83c <unknown>
+
diff --git a/llvm/test/MC/AArch64/SME2/srshl-diagnostics.s b/llvm/test/MC/AArch64/SME2/srshl-diagnostics.s
new file mode 100644
index 0000000000000..dee7d000c03d9
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/srshl-diagnostics.s
@@ -0,0 +1,50 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+srshl {z0.h-z2.h}, {z0.h-z1.h}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: srshl {z0.h-z2.h}, {z0.h-z1.h}, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+srshl {z0.s-z1.s}, {z2.s-z4.s}, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: srshl {z0.s-z1.s}, {z2.s-z4.s}, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+srshl {z20.d-z23.d}, {z20.d-z23.d}, {z8.d-z12.d}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+// CHECK-NEXT: srshl {z20.d-z23.d}, {z20.d-z23.d}, {z8.d-z12.d}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+srshl {z29.b-z30.b}, {z30.b-z31.b}, z15.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: srshl {z29.b-z30.b}, {z30.b-z31.b}, z15.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+srshl {z20.h-z23.h}, {z21.h-z24.h}, {z8.h-z11.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+// CHECK-NEXT: srshl {z20.h-z23.h}, {z21.h-z24.h}, {z8.h-z11.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+srshl {z28.b-z31.b}, {z28.b-z31.b}, {z27.b-z30.b}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+// CHECK-NEXT: srshl {z28.b-z31.b}, {z28.b-z31.b}, {z27.b-z30.b}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Single Register
+
+srshl {z20.h-z21.h}, {z20.h-z21.h}, z16.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: srshl {z20.h-z21.h}, {z20.h-z21.h}, z16.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+srshl {z0.d-z3.d}, {z0.d-z3.d}, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.d..z15.d
+// CHECK-NEXT: srshl {z0.d-z3.d}, {z0.d-z3.d}, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2/srshl.s b/llvm/test/MC/AArch64/SME2/srshl.s
new file mode 100644
index 0000000000000..1663dcc8c4705
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/srshl.s
@@ -0,0 +1,413 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+srshl {z0.h, z1.h}, {z0.h, z1.h}, z0.h // 11000001-01100000-10100010-00100000
+// CHECK-INST: srshl { z0.h, z1.h }, { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x20,0xa2,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160a220 <unknown>
+
+srshl {z20.h, z21.h}, {z20.h, z21.h}, z5.h // 11000001-01100101-10100010-00110100
+// CHECK-INST: srshl { z20.h, z21.h }, { z20.h, z21.h }, z5.h
+// CHECK-ENCODING: [0x34,0xa2,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165a234 <unknown>
+
+srshl {z22.h, z23.h}, {z22.h, z23.h}, z8.h // 11000001-01101000-10100010-00110110
+// CHECK-INST: srshl { z22.h, z23.h }, { z22.h, z23.h }, z8.h
+// CHECK-ENCODING: [0x36,0xa2,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168a236 <unknown>
+
+srshl {z30.h, z31.h}, {z30.h, z31.h}, z15.h // 11000001-01101111-10100010-00111110
+// CHECK-INST: srshl { z30.h, z31.h }, { z30.h, z31.h }, z15.h
+// CHECK-ENCODING: [0x3e,0xa2,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fa23e <unknown>
+
+
+srshl {z0.h, z1.h}, {z0.h, z1.h}, {z0.h, z1.h} // 11000001-01100000-10110010-00100000
+// CHECK-INST: srshl { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x20,0xb2,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160b220 <unknown>
+
+srshl {z20.h, z21.h}, {z20.h, z21.h}, {z20.h, z21.h} // 11000001-01110100-10110010-00110100
+// CHECK-INST: srshl { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x34,0xb2,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174b234 <unknown>
+
+srshl {z22.h, z23.h}, {z22.h, z23.h}, {z8.h, z9.h} // 11000001-01101000-10110010-00110110
+// CHECK-INST: srshl { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }
+// CHECK-ENCODING: [0x36,0xb2,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168b236 <unknown>
+
+srshl {z30.h, z31.h}, {z30.h, z31.h}, {z30.h, z31.h} // 11000001-01111110-10110010-00111110
+// CHECK-INST: srshl { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0x3e,0xb2,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17eb23e <unknown>
+
+
+srshl {z0.s, z1.s}, {z0.s, z1.s}, z0.s // 11000001-10100000-10100010-00100000
+// CHECK-INST: srshl { z0.s, z1.s }, { z0.s, z1.s }, z0.s
+// CHECK-ENCODING: [0x20,0xa2,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0a220 <unknown>
+
+srshl {z20.s, z21.s}, {z20.s, z21.s}, z5.s // 11000001-10100101-10100010-00110100
+// CHECK-INST: srshl { z20.s, z21.s }, { z20.s, z21.s }, z5.s
+// CHECK-ENCODING: [0x34,0xa2,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5a234 <unknown>
+
+srshl {z22.s, z23.s}, {z22.s, z23.s}, z8.s // 11000001-10101000-10100010-00110110
+// CHECK-INST: srshl { z22.s, z23.s }, { z22.s, z23.s }, z8.s
+// CHECK-ENCODING: [0x36,0xa2,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8a236 <unknown>
+
+srshl {z30.s, z31.s}, {z30.s, z31.s}, z15.s // 11000001-10101111-10100010-00111110
+// CHECK-INST: srshl { z30.s, z31.s }, { z30.s, z31.s }, z15.s
+// CHECK-ENCODING: [0x3e,0xa2,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afa23e <unknown>
+
+
+srshl {z0.s, z1.s}, {z0.s, z1.s}, {z0.s, z1.s} // 11000001-10100000-10110010-00100000
+// CHECK-INST: srshl { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x20,0xb2,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0b220 <unknown>
+
+srshl {z20.s, z21.s}, {z20.s, z21.s}, {z20.s, z21.s} // 11000001-10110100-10110010-00110100
+// CHECK-INST: srshl { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }
+// CHECK-ENCODING: [0x34,0xb2,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4b234 <unknown>
+
+srshl {z22.s, z23.s}, {z22.s, z23.s}, {z8.s, z9.s} // 11000001-10101000-10110010-00110110
+// CHECK-INST: srshl { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }
+// CHECK-ENCODING: [0x36,0xb2,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8b236 <unknown>
+
+srshl {z30.s, z31.s}, {z30.s, z31.s}, {z30.s, z31.s} // 11000001-10111110-10110010-00111110
+// CHECK-INST: srshl { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0x3e,0xb2,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1beb23e <unknown>
+
+
+srshl {z0.d, z1.d}, {z0.d, z1.d}, z0.d // 11000001-11100000-10100010-00100000
+// CHECK-INST: srshl { z0.d, z1.d }, { z0.d, z1.d }, z0.d
+// CHECK-ENCODING: [0x20,0xa2,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0a220 <unknown>
+
+srshl {z20.d, z21.d}, {z20.d, z21.d}, z5.d // 11000001-11100101-10100010-00110100
+// CHECK-INST: srshl { z20.d, z21.d }, { z20.d, z21.d }, z5.d
+// CHECK-ENCODING: [0x34,0xa2,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5a234 <unknown>
+
+srshl {z22.d, z23.d}, {z22.d, z23.d}, z8.d // 11000001-11101000-10100010-00110110
+// CHECK-INST: srshl { z22.d, z23.d }, { z22.d, z23.d }, z8.d
+// CHECK-ENCODING: [0x36,0xa2,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8a236 <unknown>
+
+srshl {z30.d, z31.d}, {z30.d, z31.d}, z15.d // 11000001-11101111-10100010-00111110
+// CHECK-INST: srshl { z30.d, z31.d }, { z30.d, z31.d }, z15.d
+// CHECK-ENCODING: [0x3e,0xa2,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efa23e <unknown>
+
+
+srshl {z0.d, z1.d}, {z0.d, z1.d}, {z0.d, z1.d} // 11000001-11100000-10110010-00100000
+// CHECK-INST: srshl { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }
+// CHECK-ENCODING: [0x20,0xb2,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0b220 <unknown>
+
+srshl {z20.d, z21.d}, {z20.d, z21.d}, {z20.d, z21.d} // 11000001-11110100-10110010-00110100
+// CHECK-INST: srshl { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }
+// CHECK-ENCODING: [0x34,0xb2,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4b234 <unknown>
+
+srshl {z22.d, z23.d}, {z22.d, z23.d}, {z8.d, z9.d} // 11000001-11101000-10110010-00110110
+// CHECK-INST: srshl { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }
+// CHECK-ENCODING: [0x36,0xb2,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8b236 <unknown>
+
+srshl {z30.d, z31.d}, {z30.d, z31.d}, {z30.d, z31.d} // 11000001-11111110-10110010-00111110
+// CHECK-INST: srshl { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0x3e,0xb2,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1feb23e <unknown>
+
+
+srshl {z0.b, z1.b}, {z0.b, z1.b}, z0.b // 11000001-00100000-10100010-00100000
+// CHECK-INST: srshl { z0.b, z1.b }, { z0.b, z1.b }, z0.b
+// CHECK-ENCODING: [0x20,0xa2,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120a220 <unknown>
+
+srshl {z20.b, z21.b}, {z20.b, z21.b}, z5.b // 11000001-00100101-10100010-00110100
+// CHECK-INST: srshl { z20.b, z21.b }, { z20.b, z21.b }, z5.b
+// CHECK-ENCODING: [0x34,0xa2,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c125a234 <unknown>
+
+srshl {z22.b, z23.b}, {z22.b, z23.b}, z8.b // 11000001-00101000-10100010-00110110
+// CHECK-INST: srshl { z22.b, z23.b }, { z22.b, z23.b }, z8.b
+// CHECK-ENCODING: [0x36,0xa2,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128a236 <unknown>
+
+srshl {z30.b, z31.b}, {z30.b, z31.b}, z15.b // 11000001-00101111-10100010-00111110
+// CHECK-INST: srshl { z30.b, z31.b }, { z30.b, z31.b }, z15.b
+// CHECK-ENCODING: [0x3e,0xa2,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12fa23e <unknown>
+
+
+srshl {z0.b, z1.b}, {z0.b, z1.b}, {z0.b, z1.b} // 11000001-00100000-10110010-00100000
+// CHECK-INST: srshl { z0.b, z1.b }, { z0.b, z1.b }, { z0.b, z1.b }
+// CHECK-ENCODING: [0x20,0xb2,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120b220 <unknown>
+
+srshl {z20.b, z21.b}, {z20.b, z21.b}, {z20.b, z21.b} // 11000001-00110100-10110010-00110100
+// CHECK-INST: srshl { z20.b, z21.b }, { z20.b, z21.b }, { z20.b, z21.b }
+// CHECK-ENCODING: [0x34,0xb2,0x34,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c134b234 <unknown>
+
+srshl {z22.b, z23.b}, {z22.b, z23.b}, {z8.b, z9.b} // 11000001-00101000-10110010-00110110
+// CHECK-INST: srshl { z22.b, z23.b }, { z22.b, z23.b }, { z8.b, z9.b }
+// CHECK-ENCODING: [0x36,0xb2,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128b236 <unknown>
+
+srshl {z30.b, z31.b}, {z30.b, z31.b}, {z30.b, z31.b} // 11000001-00111110-10110010-00111110
+// CHECK-INST: srshl { z30.b, z31.b }, { z30.b, z31.b }, { z30.b, z31.b }
+// CHECK-ENCODING: [0x3e,0xb2,0x3e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13eb23e <unknown>
+
+
+srshl {z0.h - z3.h}, {z0.h - z3.h}, z0.h // 11000001-01100000-10101010-00100000
+// CHECK-INST: srshl { z0.h - z3.h }, { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x20,0xaa,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160aa20 <unknown>
+
+srshl {z20.h - z23.h}, {z20.h - z23.h}, z5.h // 11000001-01100101-10101010-00110100
+// CHECK-INST: srshl { z20.h - z23.h }, { z20.h - z23.h }, z5.h
+// CHECK-ENCODING: [0x34,0xaa,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165aa34 <unknown>
+
+srshl {z20.h - z23.h}, {z20.h - z23.h}, z8.h // 11000001-01101000-10101010-00110100
+// CHECK-INST: srshl { z20.h - z23.h }, { z20.h - z23.h }, z8.h
+// CHECK-ENCODING: [0x34,0xaa,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168aa34 <unknown>
+
+srshl {z28.h - z31.h}, {z28.h - z31.h}, z15.h // 11000001-01101111-10101010-00111100
+// CHECK-INST: srshl { z28.h - z31.h }, { z28.h - z31.h }, z15.h
+// CHECK-ENCODING: [0x3c,0xaa,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16faa3c <unknown>
+
+
+srshl {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h} // 11000001-01100000-10111010-00100000
+// CHECK-INST: srshl { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x20,0xba,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160ba20 <unknown>
+
+srshl {z20.h - z23.h}, {z20.h - z23.h}, {z20.h - z23.h} // 11000001-01110100-10111010-00110100
+// CHECK-INST: srshl { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x34,0xba,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174ba34 <unknown>
+
+srshl {z20.h - z23.h}, {z20.h - z23.h}, {z8.h - z11.h} // 11000001-01101000-10111010-00110100
+// CHECK-INST: srshl { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x34,0xba,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168ba34 <unknown>
+
+srshl {z28.h - z31.h}, {z28.h - z31.h}, {z28.h - z31.h} // 11000001-01111100-10111010-00111100
+// CHECK-INST: srshl { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x3c,0xba,0x7c,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17cba3c <unknown>
+
+
+srshl {z0.s - z3.s}, {z0.s - z3.s}, z0.s // 11000001-10100000-10101010-00100000
+// CHECK-INST: srshl { z0.s - z3.s }, { z0.s - z3.s }, z0.s
+// CHECK-ENCODING: [0x20,0xaa,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0aa20 <unknown>
+
+srshl {z20.s - z23.s}, {z20.s - z23.s}, z5.s // 11000001-10100101-10101010-00110100
+// CHECK-INST: srshl { z20.s - z23.s }, { z20.s - z23.s }, z5.s
+// CHECK-ENCODING: [0x34,0xaa,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5aa34 <unknown>
+
+srshl {z20.s - z23.s}, {z20.s - z23.s}, z8.s // 11000001-10101000-10101010-00110100
+// CHECK-INST: srshl { z20.s - z23.s }, { z20.s - z23.s }, z8.s
+// CHECK-ENCODING: [0x34,0xaa,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8aa34 <unknown>
+
+srshl {z28.s - z31.s}, {z28.s - z31.s}, z15.s // 11000001-10101111-10101010-00111100
+// CHECK-INST: srshl { z28.s - z31.s }, { z28.s - z31.s }, z15.s
+// CHECK-ENCODING: [0x3c,0xaa,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afaa3c <unknown>
+
+
+srshl {z0.s - z3.s}, {z0.s - z3.s}, {z0.s - z3.s} // 11000001-10100000-10111010-00100000
+// CHECK-INST: srshl { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x20,0xba,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0ba20 <unknown>
+
+srshl {z20.s - z23.s}, {z20.s - z23.s}, {z20.s - z23.s} // 11000001-10110100-10111010-00110100
+// CHECK-INST: srshl { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }
+// CHECK-ENCODING: [0x34,0xba,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4ba34 <unknown>
+
+srshl {z20.s - z23.s}, {z20.s - z23.s}, {z8.s - z11.s} // 11000001-10101000-10111010-00110100
+// CHECK-INST: srshl { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x34,0xba,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8ba34 <unknown>
+
+srshl {z28.s - z31.s}, {z28.s - z31.s}, {z28.s - z31.s} // 11000001-10111100-10111010-00111100
+// CHECK-INST: srshl { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x3c,0xba,0xbc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bcba3c <unknown>
+
+
+srshl {z0.d - z3.d}, {z0.d - z3.d}, z0.d // 11000001-11100000-10101010-00100000
+// CHECK-INST: srshl { z0.d - z3.d }, { z0.d - z3.d }, z0.d
+// CHECK-ENCODING: [0x20,0xaa,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0aa20 <unknown>
+
+srshl {z20.d - z23.d}, {z20.d - z23.d}, z5.d // 11000001-11100101-10101010-00110100
+// CHECK-INST: srshl { z20.d - z23.d }, { z20.d - z23.d }, z5.d
+// CHECK-ENCODING: [0x34,0xaa,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5aa34 <unknown>
+
+srshl {z20.d - z23.d}, {z20.d - z23.d}, z8.d // 11000001-11101000-10101010-00110100
+// CHECK-INST: srshl { z20.d - z23.d }, { z20.d - z23.d }, z8.d
+// CHECK-ENCODING: [0x34,0xaa,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8aa34 <unknown>
+
+srshl {z28.d - z31.d}, {z28.d - z31.d}, z15.d // 11000001-11101111-10101010-00111100
+// CHECK-INST: srshl { z28.d - z31.d }, { z28.d - z31.d }, z15.d
+// CHECK-ENCODING: [0x3c,0xaa,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efaa3c <unknown>
+
+
+srshl {z0.d - z3.d}, {z0.d - z3.d}, {z0.d - z3.d} // 11000001-11100000-10111010-00100000
+// CHECK-INST: srshl { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x20,0xba,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0ba20 <unknown>
+
+srshl {z20.d - z23.d}, {z20.d - z23.d}, {z20.d - z23.d} // 11000001-11110100-10111010-00110100
+// CHECK-INST: srshl { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x34,0xba,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4ba34 <unknown>
+
+srshl {z20.d - z23.d}, {z20.d - z23.d}, {z8.d - z11.d} // 11000001-11101000-10111010-00110100
+// CHECK-INST: srshl { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x34,0xba,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8ba34 <unknown>
+
+srshl {z28.d - z31.d}, {z28.d - z31.d}, {z28.d - z31.d} // 11000001-11111100-10111010-00111100
+// CHECK-INST: srshl { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x3c,0xba,0xfc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fcba3c <unknown>
+
+
+srshl {z0.b - z3.b}, {z0.b - z3.b}, z0.b // 11000001-00100000-10101010-00100000
+// CHECK-INST: srshl { z0.b - z3.b }, { z0.b - z3.b }, z0.b
+// CHECK-ENCODING: [0x20,0xaa,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120aa20 <unknown>
+
+srshl {z20.b - z23.b}, {z20.b - z23.b}, z5.b // 11000001-00100101-10101010-00110100
+// CHECK-INST: srshl { z20.b - z23.b }, { z20.b - z23.b }, z5.b
+// CHECK-ENCODING: [0x34,0xaa,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c125aa34 <unknown>
+
+srshl {z20.b - z23.b}, {z20.b - z23.b}, z8.b // 11000001-00101000-10101010-00110100
+// CHECK-INST: srshl { z20.b - z23.b }, { z20.b - z23.b }, z8.b
+// CHECK-ENCODING: [0x34,0xaa,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128aa34 <unknown>
+
+srshl {z28.b - z31.b}, {z28.b - z31.b}, z15.b // 11000001-00101111-10101010-00111100
+// CHECK-INST: srshl { z28.b - z31.b }, { z28.b - z31.b }, z15.b
+// CHECK-ENCODING: [0x3c,0xaa,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12faa3c <unknown>
+
+
+srshl {z0.b - z3.b}, {z0.b - z3.b}, {z0.b - z3.b} // 11000001-00100000-10111010-00100000
+// CHECK-INST: srshl { z0.b - z3.b }, { z0.b - z3.b }, { z0.b - z3.b }
+// CHECK-ENCODING: [0x20,0xba,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120ba20 <unknown>
+
+srshl {z20.b - z23.b}, {z20.b - z23.b}, {z20.b - z23.b} // 11000001-00110100-10111010-00110100
+// CHECK-INST: srshl { z20.b - z23.b }, { z20.b - z23.b }, { z20.b - z23.b }
+// CHECK-ENCODING: [0x34,0xba,0x34,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c134ba34 <unknown>
+
+srshl {z20.b - z23.b}, {z20.b - z23.b}, {z8.b - z11.b} // 11000001-00101000-10111010-00110100
+// CHECK-INST: srshl { z20.b - z23.b }, { z20.b - z23.b }, { z8.b - z11.b }
+// CHECK-ENCODING: [0x34,0xba,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128ba34 <unknown>
+
+srshl {z28.b - z31.b}, {z28.b - z31.b}, {z28.b - z31.b} // 11000001-00111100-10111010-00111100
+// CHECK-INST: srshl { z28.b - z31.b }, { z28.b - z31.b }, { z28.b - z31.b }
+// CHECK-ENCODING: [0x3c,0xba,0x3c,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13cba3c <unknown>
+
diff --git a/llvm/test/MC/AArch64/SME2/umax-diagnostics.s b/llvm/test/MC/AArch64/SME2/umax-diagnostics.s
new file mode 100644
index 0000000000000..617350438b27e
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/umax-diagnostics.s
@@ -0,0 +1,30 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+umax {z0.h, z1.h}, {z0.h-z2.h}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: umax {z0.h, z1.h}, {z0.h-z2.h}, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umax {z1.d-z2.d}, {z0.d, z1.d}, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element type
+// CHECK-NEXT: umax {z1.d-z2.d}, {z0.d, z1.d}, z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid single register
+
+umax {z0.b, z1.b}, {z2.b-z3.b}, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
+// CHECK-NEXT: umax {z0.b, z1.b}, {z2.b-z3.b}, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+umax {z0.b, z1.b}, {z2.b-z3.b}, z14.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
+// CHECK-NEXT: umax {z0.b, z1.b}, {z2.b-z3.b}, z14.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2/umax.s b/llvm/test/MC/AArch64/SME2/umax.s
new file mode 100644
index 0000000000000..60d1dbb32a0a1
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/umax.s
@@ -0,0 +1,413 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+umax {z0.h, z1.h}, {z0.h, z1.h}, z0.h // 11000001-01100000-10100000-00000001
+// CHECK-INST: umax { z0.h, z1.h }, { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x01,0xa0,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160a001 <unknown>
+
+umax {z20.h, z21.h}, {z20.h, z21.h}, z5.h // 11000001-01100101-10100000-00010101
+// CHECK-INST: umax { z20.h, z21.h }, { z20.h, z21.h }, z5.h
+// CHECK-ENCODING: [0x15,0xa0,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165a015 <unknown>
+
+umax {z22.h, z23.h}, {z22.h, z23.h}, z8.h // 11000001-01101000-10100000-00010111
+// CHECK-INST: umax { z22.h, z23.h }, { z22.h, z23.h }, z8.h
+// CHECK-ENCODING: [0x17,0xa0,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168a017 <unknown>
+
+umax {z30.h, z31.h}, {z30.h, z31.h}, z15.h // 11000001-01101111-10100000-00011111
+// CHECK-INST: umax { z30.h, z31.h }, { z30.h, z31.h }, z15.h
+// CHECK-ENCODING: [0x1f,0xa0,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fa01f <unknown>
+
+
+umax {z0.h, z1.h}, {z0.h, z1.h}, {z0.h, z1.h} // 11000001-01100000-10110000-00000001
+// CHECK-INST: umax { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x01,0xb0,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160b001 <unknown>
+
+umax {z20.h, z21.h}, {z20.h, z21.h}, {z20.h, z21.h} // 11000001-01110100-10110000-00010101
+// CHECK-INST: umax { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x15,0xb0,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174b015 <unknown>
+
+umax {z22.h, z23.h}, {z22.h, z23.h}, {z8.h, z9.h} // 11000001-01101000-10110000-00010111
+// CHECK-INST: umax { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }
+// CHECK-ENCODING: [0x17,0xb0,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168b017 <unknown>
+
+umax {z30.h, z31.h}, {z30.h, z31.h}, {z30.h, z31.h} // 11000001-01111110-10110000-00011111
+// CHECK-INST: umax { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0x1f,0xb0,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17eb01f <unknown>
+
+
+umax {z0.s, z1.s}, {z0.s, z1.s}, z0.s // 11000001-10100000-10100000-00000001
+// CHECK-INST: umax { z0.s, z1.s }, { z0.s, z1.s }, z0.s
+// CHECK-ENCODING: [0x01,0xa0,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0a001 <unknown>
+
+umax {z20.s, z21.s}, {z20.s, z21.s}, z5.s // 11000001-10100101-10100000-00010101
+// CHECK-INST: umax { z20.s, z21.s }, { z20.s, z21.s }, z5.s
+// CHECK-ENCODING: [0x15,0xa0,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5a015 <unknown>
+
+umax {z22.s, z23.s}, {z22.s, z23.s}, z8.s // 11000001-10101000-10100000-00010111
+// CHECK-INST: umax { z22.s, z23.s }, { z22.s, z23.s }, z8.s
+// CHECK-ENCODING: [0x17,0xa0,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8a017 <unknown>
+
+umax {z30.s, z31.s}, {z30.s, z31.s}, z15.s // 11000001-10101111-10100000-00011111
+// CHECK-INST: umax { z30.s, z31.s }, { z30.s, z31.s }, z15.s
+// CHECK-ENCODING: [0x1f,0xa0,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afa01f <unknown>
+
+
+umax {z0.s, z1.s}, {z0.s, z1.s}, {z0.s, z1.s} // 11000001-10100000-10110000-00000001
+// CHECK-INST: umax { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x01,0xb0,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0b001 <unknown>
+
+umax {z20.s, z21.s}, {z20.s, z21.s}, {z20.s, z21.s} // 11000001-10110100-10110000-00010101
+// CHECK-INST: umax { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }
+// CHECK-ENCODING: [0x15,0xb0,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4b015 <unknown>
+
+umax {z22.s, z23.s}, {z22.s, z23.s}, {z8.s, z9.s} // 11000001-10101000-10110000-00010111
+// CHECK-INST: umax { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }
+// CHECK-ENCODING: [0x17,0xb0,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8b017 <unknown>
+
+umax {z30.s, z31.s}, {z30.s, z31.s}, {z30.s, z31.s} // 11000001-10111110-10110000-00011111
+// CHECK-INST: umax { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0x1f,0xb0,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1beb01f <unknown>
+
+
+umax {z0.d, z1.d}, {z0.d, z1.d}, z0.d // 11000001-11100000-10100000-00000001
+// CHECK-INST: umax { z0.d, z1.d }, { z0.d, z1.d }, z0.d
+// CHECK-ENCODING: [0x01,0xa0,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0a001 <unknown>
+
+umax {z20.d, z21.d}, {z20.d, z21.d}, z5.d // 11000001-11100101-10100000-00010101
+// CHECK-INST: umax { z20.d, z21.d }, { z20.d, z21.d }, z5.d
+// CHECK-ENCODING: [0x15,0xa0,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5a015 <unknown>
+
+umax {z22.d, z23.d}, {z22.d, z23.d}, z8.d // 11000001-11101000-10100000-00010111
+// CHECK-INST: umax { z22.d, z23.d }, { z22.d, z23.d }, z8.d
+// CHECK-ENCODING: [0x17,0xa0,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8a017 <unknown>
+
+umax {z30.d, z31.d}, {z30.d, z31.d}, z15.d // 11000001-11101111-10100000-00011111
+// CHECK-INST: umax { z30.d, z31.d }, { z30.d, z31.d }, z15.d
+// CHECK-ENCODING: [0x1f,0xa0,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efa01f <unknown>
+
+
+umax {z0.d, z1.d}, {z0.d, z1.d}, {z0.d, z1.d} // 11000001-11100000-10110000-00000001
+// CHECK-INST: umax { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }
+// CHECK-ENCODING: [0x01,0xb0,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0b001 <unknown>
+
+umax {z20.d, z21.d}, {z20.d, z21.d}, {z20.d, z21.d} // 11000001-11110100-10110000-00010101
+// CHECK-INST: umax { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }
+// CHECK-ENCODING: [0x15,0xb0,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4b015 <unknown>
+
+umax {z22.d, z23.d}, {z22.d, z23.d}, {z8.d, z9.d} // 11000001-11101000-10110000-00010111
+// CHECK-INST: umax { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }
+// CHECK-ENCODING: [0x17,0xb0,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8b017 <unknown>
+
+umax {z30.d, z31.d}, {z30.d, z31.d}, {z30.d, z31.d} // 11000001-11111110-10110000-00011111
+// CHECK-INST: umax { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0x1f,0xb0,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1feb01f <unknown>
+
+
+umax {z0.b, z1.b}, {z0.b, z1.b}, z0.b // 11000001-00100000-10100000-00000001
+// CHECK-INST: umax { z0.b, z1.b }, { z0.b, z1.b }, z0.b
+// CHECK-ENCODING: [0x01,0xa0,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120a001 <unknown>
+
+umax {z20.b, z21.b}, {z20.b, z21.b}, z5.b // 11000001-00100101-10100000-00010101
+// CHECK-INST: umax { z20.b, z21.b }, { z20.b, z21.b }, z5.b
+// CHECK-ENCODING: [0x15,0xa0,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c125a015 <unknown>
+
+umax {z22.b, z23.b}, {z22.b, z23.b}, z8.b // 11000001-00101000-10100000-00010111
+// CHECK-INST: umax { z22.b, z23.b }, { z22.b, z23.b }, z8.b
+// CHECK-ENCODING: [0x17,0xa0,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128a017 <unknown>
+
+umax {z30.b, z31.b}, {z30.b, z31.b}, z15.b // 11000001-00101111-10100000-00011111
+// CHECK-INST: umax { z30.b, z31.b }, { z30.b, z31.b }, z15.b
+// CHECK-ENCODING: [0x1f,0xa0,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12fa01f <unknown>
+
+
+umax {z0.b, z1.b}, {z0.b, z1.b}, {z0.b, z1.b} // 11000001-00100000-10110000-00000001
+// CHECK-INST: umax { z0.b, z1.b }, { z0.b, z1.b }, { z0.b, z1.b }
+// CHECK-ENCODING: [0x01,0xb0,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120b001 <unknown>
+
+umax {z20.b, z21.b}, {z20.b, z21.b}, {z20.b, z21.b} // 11000001-00110100-10110000-00010101
+// CHECK-INST: umax { z20.b, z21.b }, { z20.b, z21.b }, { z20.b, z21.b }
+// CHECK-ENCODING: [0x15,0xb0,0x34,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c134b015 <unknown>
+
+umax {z22.b, z23.b}, {z22.b, z23.b}, {z8.b, z9.b} // 11000001-00101000-10110000-00010111
+// CHECK-INST: umax { z22.b, z23.b }, { z22.b, z23.b }, { z8.b, z9.b }
+// CHECK-ENCODING: [0x17,0xb0,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128b017 <unknown>
+
+umax {z30.b, z31.b}, {z30.b, z31.b}, {z30.b, z31.b} // 11000001-00111110-10110000-00011111
+// CHECK-INST: umax { z30.b, z31.b }, { z30.b, z31.b }, { z30.b, z31.b }
+// CHECK-ENCODING: [0x1f,0xb0,0x3e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13eb01f <unknown>
+
+
+umax {z0.h - z3.h}, {z0.h - z3.h}, z0.h // 11000001-01100000-10101000-00000001
+// CHECK-INST: umax { z0.h - z3.h }, { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x01,0xa8,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160a801 <unknown>
+
+umax {z20.h - z23.h}, {z20.h - z23.h}, z5.h // 11000001-01100101-10101000-00010101
+// CHECK-INST: umax { z20.h - z23.h }, { z20.h - z23.h }, z5.h
+// CHECK-ENCODING: [0x15,0xa8,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165a815 <unknown>
+
+umax {z20.h - z23.h}, {z20.h - z23.h}, z8.h // 11000001-01101000-10101000-00010101
+// CHECK-INST: umax { z20.h - z23.h }, { z20.h - z23.h }, z8.h
+// CHECK-ENCODING: [0x15,0xa8,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168a815 <unknown>
+
+umax {z28.h - z31.h}, {z28.h - z31.h}, z15.h // 11000001-01101111-10101000-00011101
+// CHECK-INST: umax { z28.h - z31.h }, { z28.h - z31.h }, z15.h
+// CHECK-ENCODING: [0x1d,0xa8,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fa81d <unknown>
+
+
+umax {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h} // 11000001-01100000-10111000-00000001
+// CHECK-INST: umax { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x01,0xb8,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160b801 <unknown>
+
+umax {z20.h - z23.h}, {z20.h - z23.h}, {z20.h - z23.h} // 11000001-01110100-10111000-00010101
+// CHECK-INST: umax { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x15,0xb8,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174b815 <unknown>
+
+umax {z20.h - z23.h}, {z20.h - z23.h}, {z8.h - z11.h} // 11000001-01101000-10111000-00010101
+// CHECK-INST: umax { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x15,0xb8,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168b815 <unknown>
+
+umax {z28.h - z31.h}, {z28.h - z31.h}, {z28.h - z31.h} // 11000001-01111100-10111000-00011101
+// CHECK-INST: umax { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x1d,0xb8,0x7c,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17cb81d <unknown>
+
+
+umax {z0.s - z3.s}, {z0.s - z3.s}, z0.s // 11000001-10100000-10101000-00000001
+// CHECK-INST: umax { z0.s - z3.s }, { z0.s - z3.s }, z0.s
+// CHECK-ENCODING: [0x01,0xa8,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0a801 <unknown>
+
+umax {z20.s - z23.s}, {z20.s - z23.s}, z5.s // 11000001-10100101-10101000-00010101
+// CHECK-INST: umax { z20.s - z23.s }, { z20.s - z23.s }, z5.s
+// CHECK-ENCODING: [0x15,0xa8,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5a815 <unknown>
+
+umax {z20.s - z23.s}, {z20.s - z23.s}, z8.s // 11000001-10101000-10101000-00010101
+// CHECK-INST: umax { z20.s - z23.s }, { z20.s - z23.s }, z8.s
+// CHECK-ENCODING: [0x15,0xa8,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8a815 <unknown>
+
+umax {z28.s - z31.s}, {z28.s - z31.s}, z15.s // 11000001-10101111-10101000-00011101
+// CHECK-INST: umax { z28.s - z31.s }, { z28.s - z31.s }, z15.s
+// CHECK-ENCODING: [0x1d,0xa8,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afa81d <unknown>
+
+
+umax {z0.s - z3.s}, {z0.s - z3.s}, {z0.s - z3.s} // 11000001-10100000-10111000-00000001
+// CHECK-INST: umax { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x01,0xb8,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0b801 <unknown>
+
+umax {z20.s - z23.s}, {z20.s - z23.s}, {z20.s - z23.s} // 11000001-10110100-10111000-00010101
+// CHECK-INST: umax { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }
+// CHECK-ENCODING: [0x15,0xb8,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4b815 <unknown>
+
+umax {z20.s - z23.s}, {z20.s - z23.s}, {z8.s - z11.s} // 11000001-10101000-10111000-00010101
+// CHECK-INST: umax { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x15,0xb8,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8b815 <unknown>
+
+umax {z28.s - z31.s}, {z28.s - z31.s}, {z28.s - z31.s} // 11000001-10111100-10111000-00011101
+// CHECK-INST: umax { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x1d,0xb8,0xbc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bcb81d <unknown>
+
+
+umax {z0.d - z3.d}, {z0.d - z3.d}, z0.d // 11000001-11100000-10101000-00000001
+// CHECK-INST: umax { z0.d - z3.d }, { z0.d - z3.d }, z0.d
+// CHECK-ENCODING: [0x01,0xa8,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0a801 <unknown>
+
+umax {z20.d - z23.d}, {z20.d - z23.d}, z5.d // 11000001-11100101-10101000-00010101
+// CHECK-INST: umax { z20.d - z23.d }, { z20.d - z23.d }, z5.d
+// CHECK-ENCODING: [0x15,0xa8,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5a815 <unknown>
+
+umax {z20.d - z23.d}, {z20.d - z23.d}, z8.d // 11000001-11101000-10101000-00010101
+// CHECK-INST: umax { z20.d - z23.d }, { z20.d - z23.d }, z8.d
+// CHECK-ENCODING: [0x15,0xa8,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8a815 <unknown>
+
+umax {z28.d - z31.d}, {z28.d - z31.d}, z15.d // 11000001-11101111-10101000-00011101
+// CHECK-INST: umax { z28.d - z31.d }, { z28.d - z31.d }, z15.d
+// CHECK-ENCODING: [0x1d,0xa8,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efa81d <unknown>
+
+
+umax {z0.d - z3.d}, {z0.d - z3.d}, {z0.d - z3.d} // 11000001-11100000-10111000-00000001
+// CHECK-INST: umax { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x01,0xb8,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0b801 <unknown>
+
+umax {z20.d - z23.d}, {z20.d - z23.d}, {z20.d - z23.d} // 11000001-11110100-10111000-00010101
+// CHECK-INST: umax { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x15,0xb8,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4b815 <unknown>
+
+umax {z20.d - z23.d}, {z20.d - z23.d}, {z8.d - z11.d} // 11000001-11101000-10111000-00010101
+// CHECK-INST: umax { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x15,0xb8,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8b815 <unknown>
+
+umax {z28.d - z31.d}, {z28.d - z31.d}, {z28.d - z31.d} // 11000001-11111100-10111000-00011101
+// CHECK-INST: umax { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x1d,0xb8,0xfc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fcb81d <unknown>
+
+
+umax {z0.b - z3.b}, {z0.b - z3.b}, z0.b // 11000001-00100000-10101000-00000001
+// CHECK-INST: umax { z0.b - z3.b }, { z0.b - z3.b }, z0.b
+// CHECK-ENCODING: [0x01,0xa8,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120a801 <unknown>
+
+umax {z20.b - z23.b}, {z20.b - z23.b}, z5.b // 11000001-00100101-10101000-00010101
+// CHECK-INST: umax { z20.b - z23.b }, { z20.b - z23.b }, z5.b
+// CHECK-ENCODING: [0x15,0xa8,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c125a815 <unknown>
+
+umax {z20.b - z23.b}, {z20.b - z23.b}, z8.b // 11000001-00101000-10101000-00010101
+// CHECK-INST: umax { z20.b - z23.b }, { z20.b - z23.b }, z8.b
+// CHECK-ENCODING: [0x15,0xa8,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128a815 <unknown>
+
+umax {z28.b - z31.b}, {z28.b - z31.b}, z15.b // 11000001-00101111-10101000-00011101
+// CHECK-INST: umax { z28.b - z31.b }, { z28.b - z31.b }, z15.b
+// CHECK-ENCODING: [0x1d,0xa8,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12fa81d <unknown>
+
+
+umax {z0.b - z3.b}, {z0.b - z3.b}, {z0.b - z3.b} // 11000001-00100000-10111000-00000001
+// CHECK-INST: umax { z0.b - z3.b }, { z0.b - z3.b }, { z0.b - z3.b }
+// CHECK-ENCODING: [0x01,0xb8,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120b801 <unknown>
+
+umax {z20.b - z23.b}, {z20.b - z23.b}, {z20.b - z23.b} // 11000001-00110100-10111000-00010101
+// CHECK-INST: umax { z20.b - z23.b }, { z20.b - z23.b }, { z20.b - z23.b }
+// CHECK-ENCODING: [0x15,0xb8,0x34,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c134b815 <unknown>
+
+umax {z20.b - z23.b}, {z20.b - z23.b}, {z8.b - z11.b} // 11000001-00101000-10111000-00010101
+// CHECK-INST: umax { z20.b - z23.b }, { z20.b - z23.b }, { z8.b - z11.b }
+// CHECK-ENCODING: [0x15,0xb8,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128b815 <unknown>
+
+umax {z28.b - z31.b}, {z28.b - z31.b}, {z28.b - z31.b} // 11000001-00111100-10111000-00011101
+// CHECK-INST: umax { z28.b - z31.b }, { z28.b - z31.b }, { z28.b - z31.b }
+// CHECK-ENCODING: [0x1d,0xb8,0x3c,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13cb81d <unknown>
+
diff --git a/llvm/test/MC/AArch64/SME2/umin-diagnostics.s b/llvm/test/MC/AArch64/SME2/umin-diagnostics.s
new file mode 100644
index 0000000000000..3d6217da8f6da
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/umin-diagnostics.s
@@ -0,0 +1,30 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+umin {z0.h, z1.h}, {z0.h-z2.h}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: umin {z0.h, z1.h}, {z0.h-z2.h}, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umin {z1.d-z2.d}, {z0.d, z1.d}, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element type
+// CHECK-NEXT: umin {z1.d-z2.d}, {z0.d, z1.d}, z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid single register
+
+umin {z0.b, z1.b}, {z2.b-z3.b}, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
+// CHECK-NEXT: umin {z0.b, z1.b}, {z2.b-z3.b}, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+umin {z0.b, z1.b}, {z2.b-z3.b}, z14.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
+// CHECK-NEXT: umin {z0.b, z1.b}, {z2.b-z3.b}, z14.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2/umin.s b/llvm/test/MC/AArch64/SME2/umin.s
new file mode 100644
index 0000000000000..b87b9f7f99d10
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/umin.s
@@ -0,0 +1,413 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+umin {z0.h, z1.h}, {z0.h, z1.h}, z0.h // 11000001-01100000-10100000-00100001
+// CHECK-INST: umin { z0.h, z1.h }, { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x21,0xa0,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160a021 <unknown>
+
+umin {z20.h, z21.h}, {z20.h, z21.h}, z5.h // 11000001-01100101-10100000-00110101
+// CHECK-INST: umin { z20.h, z21.h }, { z20.h, z21.h }, z5.h
+// CHECK-ENCODING: [0x35,0xa0,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165a035 <unknown>
+
+umin {z22.h, z23.h}, {z22.h, z23.h}, z8.h // 11000001-01101000-10100000-00110111
+// CHECK-INST: umin { z22.h, z23.h }, { z22.h, z23.h }, z8.h
+// CHECK-ENCODING: [0x37,0xa0,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168a037 <unknown>
+
+umin {z30.h, z31.h}, {z30.h, z31.h}, z15.h // 11000001-01101111-10100000-00111111
+// CHECK-INST: umin { z30.h, z31.h }, { z30.h, z31.h }, z15.h
+// CHECK-ENCODING: [0x3f,0xa0,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fa03f <unknown>
+
+
+umin {z0.h, z1.h}, {z0.h, z1.h}, {z0.h, z1.h} // 11000001-01100000-10110000-00100001
+// CHECK-INST: umin { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x21,0xb0,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160b021 <unknown>
+
+umin {z20.h, z21.h}, {z20.h, z21.h}, {z20.h, z21.h} // 11000001-01110100-10110000-00110101
+// CHECK-INST: umin { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x35,0xb0,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174b035 <unknown>
+
+umin {z22.h, z23.h}, {z22.h, z23.h}, {z8.h, z9.h} // 11000001-01101000-10110000-00110111
+// CHECK-INST: umin { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }
+// CHECK-ENCODING: [0x37,0xb0,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168b037 <unknown>
+
+umin {z30.h, z31.h}, {z30.h, z31.h}, {z30.h, z31.h} // 11000001-01111110-10110000-00111111
+// CHECK-INST: umin { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0x3f,0xb0,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17eb03f <unknown>
+
+
+umin {z0.s, z1.s}, {z0.s, z1.s}, z0.s // 11000001-10100000-10100000-00100001
+// CHECK-INST: umin { z0.s, z1.s }, { z0.s, z1.s }, z0.s
+// CHECK-ENCODING: [0x21,0xa0,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0a021 <unknown>
+
+umin {z20.s, z21.s}, {z20.s, z21.s}, z5.s // 11000001-10100101-10100000-00110101
+// CHECK-INST: umin { z20.s, z21.s }, { z20.s, z21.s }, z5.s
+// CHECK-ENCODING: [0x35,0xa0,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5a035 <unknown>
+
+umin {z22.s, z23.s}, {z22.s, z23.s}, z8.s // 11000001-10101000-10100000-00110111
+// CHECK-INST: umin { z22.s, z23.s }, { z22.s, z23.s }, z8.s
+// CHECK-ENCODING: [0x37,0xa0,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8a037 <unknown>
+
+umin {z30.s, z31.s}, {z30.s, z31.s}, z15.s // 11000001-10101111-10100000-00111111
+// CHECK-INST: umin { z30.s, z31.s }, { z30.s, z31.s }, z15.s
+// CHECK-ENCODING: [0x3f,0xa0,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afa03f <unknown>
+
+
+umin {z0.s, z1.s}, {z0.s, z1.s}, {z0.s, z1.s} // 11000001-10100000-10110000-00100001
+// CHECK-INST: umin { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x21,0xb0,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0b021 <unknown>
+
+umin {z20.s, z21.s}, {z20.s, z21.s}, {z20.s, z21.s} // 11000001-10110100-10110000-00110101
+// CHECK-INST: umin { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }
+// CHECK-ENCODING: [0x35,0xb0,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4b035 <unknown>
+
+umin {z22.s, z23.s}, {z22.s, z23.s}, {z8.s, z9.s} // 11000001-10101000-10110000-00110111
+// CHECK-INST: umin { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }
+// CHECK-ENCODING: [0x37,0xb0,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8b037 <unknown>
+
+umin {z30.s, z31.s}, {z30.s, z31.s}, {z30.s, z31.s} // 11000001-10111110-10110000-00111111
+// CHECK-INST: umin { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0x3f,0xb0,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1beb03f <unknown>
+
+
+umin {z0.d, z1.d}, {z0.d, z1.d}, z0.d // 11000001-11100000-10100000-00100001
+// CHECK-INST: umin { z0.d, z1.d }, { z0.d, z1.d }, z0.d
+// CHECK-ENCODING: [0x21,0xa0,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0a021 <unknown>
+
+umin {z20.d, z21.d}, {z20.d, z21.d}, z5.d // 11000001-11100101-10100000-00110101
+// CHECK-INST: umin { z20.d, z21.d }, { z20.d, z21.d }, z5.d
+// CHECK-ENCODING: [0x35,0xa0,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5a035 <unknown>
+
+umin {z22.d, z23.d}, {z22.d, z23.d}, z8.d // 11000001-11101000-10100000-00110111
+// CHECK-INST: umin { z22.d, z23.d }, { z22.d, z23.d }, z8.d
+// CHECK-ENCODING: [0x37,0xa0,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8a037 <unknown>
+
+umin {z30.d, z31.d}, {z30.d, z31.d}, z15.d // 11000001-11101111-10100000-00111111
+// CHECK-INST: umin { z30.d, z31.d }, { z30.d, z31.d }, z15.d
+// CHECK-ENCODING: [0x3f,0xa0,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efa03f <unknown>
+
+
+umin {z0.d, z1.d}, {z0.d, z1.d}, {z0.d, z1.d} // 11000001-11100000-10110000-00100001
+// CHECK-INST: umin { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }
+// CHECK-ENCODING: [0x21,0xb0,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0b021 <unknown>
+
+umin {z20.d, z21.d}, {z20.d, z21.d}, {z20.d, z21.d} // 11000001-11110100-10110000-00110101
+// CHECK-INST: umin { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }
+// CHECK-ENCODING: [0x35,0xb0,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4b035 <unknown>
+
+umin {z22.d, z23.d}, {z22.d, z23.d}, {z8.d, z9.d} // 11000001-11101000-10110000-00110111
+// CHECK-INST: umin { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }
+// CHECK-ENCODING: [0x37,0xb0,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8b037 <unknown>
+
+umin {z30.d, z31.d}, {z30.d, z31.d}, {z30.d, z31.d} // 11000001-11111110-10110000-00111111
+// CHECK-INST: umin { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0x3f,0xb0,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1feb03f <unknown>
+
+
+umin {z0.b, z1.b}, {z0.b, z1.b}, z0.b // 11000001-00100000-10100000-00100001
+// CHECK-INST: umin { z0.b, z1.b }, { z0.b, z1.b }, z0.b
+// CHECK-ENCODING: [0x21,0xa0,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120a021 <unknown>
+
+umin {z20.b, z21.b}, {z20.b, z21.b}, z5.b // 11000001-00100101-10100000-00110101
+// CHECK-INST: umin { z20.b, z21.b }, { z20.b, z21.b }, z5.b
+// CHECK-ENCODING: [0x35,0xa0,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c125a035 <unknown>
+
+umin {z22.b, z23.b}, {z22.b, z23.b}, z8.b // 11000001-00101000-10100000-00110111
+// CHECK-INST: umin { z22.b, z23.b }, { z22.b, z23.b }, z8.b
+// CHECK-ENCODING: [0x37,0xa0,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128a037 <unknown>
+
+umin {z30.b, z31.b}, {z30.b, z31.b}, z15.b // 11000001-00101111-10100000-00111111
+// CHECK-INST: umin { z30.b, z31.b }, { z30.b, z31.b }, z15.b
+// CHECK-ENCODING: [0x3f,0xa0,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12fa03f <unknown>
+
+
+umin {z0.b, z1.b}, {z0.b, z1.b}, {z0.b, z1.b} // 11000001-00100000-10110000-00100001
+// CHECK-INST: umin { z0.b, z1.b }, { z0.b, z1.b }, { z0.b, z1.b }
+// CHECK-ENCODING: [0x21,0xb0,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120b021 <unknown>
+
+umin {z20.b, z21.b}, {z20.b, z21.b}, {z20.b, z21.b} // 11000001-00110100-10110000-00110101
+// CHECK-INST: umin { z20.b, z21.b }, { z20.b, z21.b }, { z20.b, z21.b }
+// CHECK-ENCODING: [0x35,0xb0,0x34,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c134b035 <unknown>
+
+umin {z22.b, z23.b}, {z22.b, z23.b}, {z8.b, z9.b} // 11000001-00101000-10110000-00110111
+// CHECK-INST: umin { z22.b, z23.b }, { z22.b, z23.b }, { z8.b, z9.b }
+// CHECK-ENCODING: [0x37,0xb0,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128b037 <unknown>
+
+umin {z30.b, z31.b}, {z30.b, z31.b}, {z30.b, z31.b} // 11000001-00111110-10110000-00111111
+// CHECK-INST: umin { z30.b, z31.b }, { z30.b, z31.b }, { z30.b, z31.b }
+// CHECK-ENCODING: [0x3f,0xb0,0x3e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13eb03f <unknown>
+
+
+umin {z0.h - z3.h}, {z0.h - z3.h}, z0.h // 11000001-01100000-10101000-00100001
+// CHECK-INST: umin { z0.h - z3.h }, { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x21,0xa8,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160a821 <unknown>
+
+umin {z20.h - z23.h}, {z20.h - z23.h}, z5.h // 11000001-01100101-10101000-00110101
+// CHECK-INST: umin { z20.h - z23.h }, { z20.h - z23.h }, z5.h
+// CHECK-ENCODING: [0x35,0xa8,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165a835 <unknown>
+
+umin {z20.h - z23.h}, {z20.h - z23.h}, z8.h // 11000001-01101000-10101000-00110101
+// CHECK-INST: umin { z20.h - z23.h }, { z20.h - z23.h }, z8.h
+// CHECK-ENCODING: [0x35,0xa8,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168a835 <unknown>
+
+umin {z28.h - z31.h}, {z28.h - z31.h}, z15.h // 11000001-01101111-10101000-00111101
+// CHECK-INST: umin { z28.h - z31.h }, { z28.h - z31.h }, z15.h
+// CHECK-ENCODING: [0x3d,0xa8,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fa83d <unknown>
+
+
+umin {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h} // 11000001-01100000-10111000-00100001
+// CHECK-INST: umin { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x21,0xb8,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160b821 <unknown>
+
+umin {z20.h - z23.h}, {z20.h - z23.h}, {z20.h - z23.h} // 11000001-01110100-10111000-00110101
+// CHECK-INST: umin { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x35,0xb8,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174b835 <unknown>
+
+umin {z20.h - z23.h}, {z20.h - z23.h}, {z8.h - z11.h} // 11000001-01101000-10111000-00110101
+// CHECK-INST: umin { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x35,0xb8,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168b835 <unknown>
+
+umin {z28.h - z31.h}, {z28.h - z31.h}, {z28.h - z31.h} // 11000001-01111100-10111000-00111101
+// CHECK-INST: umin { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x3d,0xb8,0x7c,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17cb83d <unknown>
+
+
+umin {z0.s - z3.s}, {z0.s - z3.s}, z0.s // 11000001-10100000-10101000-00100001
+// CHECK-INST: umin { z0.s - z3.s }, { z0.s - z3.s }, z0.s
+// CHECK-ENCODING: [0x21,0xa8,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0a821 <unknown>
+
+umin {z20.s - z23.s}, {z20.s - z23.s}, z5.s // 11000001-10100101-10101000-00110101
+// CHECK-INST: umin { z20.s - z23.s }, { z20.s - z23.s }, z5.s
+// CHECK-ENCODING: [0x35,0xa8,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5a835 <unknown>
+
+umin {z20.s - z23.s}, {z20.s - z23.s}, z8.s // 11000001-10101000-10101000-00110101
+// CHECK-INST: umin { z20.s - z23.s }, { z20.s - z23.s }, z8.s
+// CHECK-ENCODING: [0x35,0xa8,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8a835 <unknown>
+
+umin {z28.s - z31.s}, {z28.s - z31.s}, z15.s // 11000001-10101111-10101000-00111101
+// CHECK-INST: umin { z28.s - z31.s }, { z28.s - z31.s }, z15.s
+// CHECK-ENCODING: [0x3d,0xa8,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afa83d <unknown>
+
+
+umin {z0.s - z3.s}, {z0.s - z3.s}, {z0.s - z3.s} // 11000001-10100000-10111000-00100001
+// CHECK-INST: umin { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x21,0xb8,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0b821 <unknown>
+
+umin {z20.s - z23.s}, {z20.s - z23.s}, {z20.s - z23.s} // 11000001-10110100-10111000-00110101
+// CHECK-INST: umin { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }
+// CHECK-ENCODING: [0x35,0xb8,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4b835 <unknown>
+
+umin {z20.s - z23.s}, {z20.s - z23.s}, {z8.s - z11.s} // 11000001-10101000-10111000-00110101
+// CHECK-INST: umin { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x35,0xb8,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8b835 <unknown>
+
+umin {z28.s - z31.s}, {z28.s - z31.s}, {z28.s - z31.s} // 11000001-10111100-10111000-00111101
+// CHECK-INST: umin { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x3d,0xb8,0xbc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bcb83d <unknown>
+
+
+umin {z0.d - z3.d}, {z0.d - z3.d}, z0.d // 11000001-11100000-10101000-00100001
+// CHECK-INST: umin { z0.d - z3.d }, { z0.d - z3.d }, z0.d
+// CHECK-ENCODING: [0x21,0xa8,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0a821 <unknown>
+
+umin {z20.d - z23.d}, {z20.d - z23.d}, z5.d // 11000001-11100101-10101000-00110101
+// CHECK-INST: umin { z20.d - z23.d }, { z20.d - z23.d }, z5.d
+// CHECK-ENCODING: [0x35,0xa8,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5a835 <unknown>
+
+umin {z20.d - z23.d}, {z20.d - z23.d}, z8.d // 11000001-11101000-10101000-00110101
+// CHECK-INST: umin { z20.d - z23.d }, { z20.d - z23.d }, z8.d
+// CHECK-ENCODING: [0x35,0xa8,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8a835 <unknown>
+
+umin {z28.d - z31.d}, {z28.d - z31.d}, z15.d // 11000001-11101111-10101000-00111101
+// CHECK-INST: umin { z28.d - z31.d }, { z28.d - z31.d }, z15.d
+// CHECK-ENCODING: [0x3d,0xa8,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efa83d <unknown>
+
+
+umin {z0.d - z3.d}, {z0.d - z3.d}, {z0.d - z3.d} // 11000001-11100000-10111000-00100001
+// CHECK-INST: umin { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x21,0xb8,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0b821 <unknown>
+
+umin {z20.d - z23.d}, {z20.d - z23.d}, {z20.d - z23.d} // 11000001-11110100-10111000-00110101
+// CHECK-INST: umin { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x35,0xb8,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4b835 <unknown>
+
+umin {z20.d - z23.d}, {z20.d - z23.d}, {z8.d - z11.d} // 11000001-11101000-10111000-00110101
+// CHECK-INST: umin { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x35,0xb8,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8b835 <unknown>
+
+umin {z28.d - z31.d}, {z28.d - z31.d}, {z28.d - z31.d} // 11000001-11111100-10111000-00111101
+// CHECK-INST: umin { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x3d,0xb8,0xfc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fcb83d <unknown>
+
+
+umin {z0.b - z3.b}, {z0.b - z3.b}, z0.b // 11000001-00100000-10101000-00100001
+// CHECK-INST: umin { z0.b - z3.b }, { z0.b - z3.b }, z0.b
+// CHECK-ENCODING: [0x21,0xa8,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120a821 <unknown>
+
+umin {z20.b - z23.b}, {z20.b - z23.b}, z5.b // 11000001-00100101-10101000-00110101
+// CHECK-INST: umin { z20.b - z23.b }, { z20.b - z23.b }, z5.b
+// CHECK-ENCODING: [0x35,0xa8,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c125a835 <unknown>
+
+umin {z20.b - z23.b}, {z20.b - z23.b}, z8.b // 11000001-00101000-10101000-00110101
+// CHECK-INST: umin { z20.b - z23.b }, { z20.b - z23.b }, z8.b
+// CHECK-ENCODING: [0x35,0xa8,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128a835 <unknown>
+
+umin {z28.b - z31.b}, {z28.b - z31.b}, z15.b // 11000001-00101111-10101000-00111101
+// CHECK-INST: umin { z28.b - z31.b }, { z28.b - z31.b }, z15.b
+// CHECK-ENCODING: [0x3d,0xa8,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12fa83d <unknown>
+
+
+umin {z0.b - z3.b}, {z0.b - z3.b}, {z0.b - z3.b} // 11000001-00100000-10111000-00100001
+// CHECK-INST: umin { z0.b - z3.b }, { z0.b - z3.b }, { z0.b - z3.b }
+// CHECK-ENCODING: [0x21,0xb8,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120b821 <unknown>
+
+umin {z20.b - z23.b}, {z20.b - z23.b}, {z20.b - z23.b} // 11000001-00110100-10111000-00110101
+// CHECK-INST: umin { z20.b - z23.b }, { z20.b - z23.b }, { z20.b - z23.b }
+// CHECK-ENCODING: [0x35,0xb8,0x34,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c134b835 <unknown>
+
+umin {z20.b - z23.b}, {z20.b - z23.b}, {z8.b - z11.b} // 11000001-00101000-10111000-00110101
+// CHECK-INST: umin { z20.b - z23.b }, { z20.b - z23.b }, { z8.b - z11.b }
+// CHECK-ENCODING: [0x35,0xb8,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128b835 <unknown>
+
+umin {z28.b - z31.b}, {z28.b - z31.b}, {z28.b - z31.b} // 11000001-00111100-10111000-00111101
+// CHECK-INST: umin { z28.b - z31.b }, { z28.b - z31.b }, { z28.b - z31.b }
+// CHECK-ENCODING: [0x3d,0xb8,0x3c,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13cb83d <unknown>
+
diff --git a/llvm/test/MC/AArch64/SME2/urshl-diagnostics.s b/llvm/test/MC/AArch64/SME2/urshl-diagnostics.s
new file mode 100644
index 0000000000000..a715cb8aa2b76
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/urshl-diagnostics.s
@@ -0,0 +1,50 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+urshl {z0.h-z2.h}, {z0.h-z1.h}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: urshl {z0.h-z2.h}, {z0.h-z1.h}, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+urshl {z0.s-z1.s}, {z2.s-z4.s}, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: urshl {z0.s-z1.s}, {z2.s-z4.s}, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+urshl {z20.d-z23.d}, {z20.d-z23.d}, {z8.d-z12.d}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+// CHECK-NEXT: urshl {z20.d-z23.d}, {z20.d-z23.d}, {z8.d-z12.d}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+urshl {z29.b-z30.b}, {z30.b-z31.b}, z15.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: urshl {z29.b-z30.b}, {z30.b-z31.b}, z15.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+urshl {z20.h-z23.h}, {z21.h-z24.h}, {z8.h-z11.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+// CHECK-NEXT: urshl {z20.h-z23.h}, {z21.h-z24.h}, {z8.h-z11.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+urshl {z28.b-z31.b}, {z28.b-z31.b}, {z27.b-z30.b}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+// CHECK-NEXT: urshl {z28.b-z31.b}, {z28.b-z31.b}, {z27.b-z30.b}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Single Register
+
+urshl {z20.h-z21.h}, {z20.h-z21.h}, z16.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: urshl {z20.h-z21.h}, {z20.h-z21.h}, z16.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+urshl {z0.d-z3.d}, {z0.d-z3.d}, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.d..z15.d
+// CHECK-NEXT: urshl {z0.d-z3.d}, {z0.d-z3.d}, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2/urshl.s b/llvm/test/MC/AArch64/SME2/urshl.s
new file mode 100644
index 0000000000000..e6666b1aed957
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/urshl.s
@@ -0,0 +1,414 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+urshl {z0.h, z1.h}, {z0.h, z1.h}, z0.h // 11000001-01100000-10100010-00100001
+// CHECK-INST: urshl { z0.h, z1.h }, { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x21,0xa2,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160a221 <unknown>
+
+urshl {z20.h, z21.h}, {z20.h, z21.h}, z5.h // 11000001-01100101-10100010-00110101
+// CHECK-INST: urshl { z20.h, z21.h }, { z20.h, z21.h }, z5.h
+// CHECK-ENCODING: [0x35,0xa2,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165a235 <unknown>
+
+urshl {z22.h, z23.h}, {z22.h, z23.h}, z8.h // 11000001-01101000-10100010-00110111
+// CHECK-INST: urshl { z22.h, z23.h }, { z22.h, z23.h }, z8.h
+// CHECK-ENCODING: [0x37,0xa2,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168a237 <unknown>
+
+urshl {z30.h, z31.h}, {z30.h, z31.h}, z15.h // 11000001-01101111-10100010-00111111
+// CHECK-INST: urshl { z30.h, z31.h }, { z30.h, z31.h }, z15.h
+// CHECK-ENCODING: [0x3f,0xa2,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fa23f <unknown>
+
+
+urshl {z0.h, z1.h}, {z0.h, z1.h}, {z0.h, z1.h} // 11000001-01100000-10110010-00100001
+// CHECK-INST: urshl { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x21,0xb2,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160b221 <unknown>
+
+urshl {z20.h, z21.h}, {z20.h, z21.h}, {z20.h, z21.h} // 11000001-01110100-10110010-00110101
+// CHECK-INST: urshl { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x35,0xb2,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174b235 <unknown>
+
+urshl {z22.h, z23.h}, {z22.h, z23.h}, {z8.h, z9.h} // 11000001-01101000-10110010-00110111
+// CHECK-INST: urshl { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }
+// CHECK-ENCODING: [0x37,0xb2,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168b237 <unknown>
+
+urshl {z30.h, z31.h}, {z30.h, z31.h}, {z30.h, z31.h} // 11000001-01111110-10110010-00111111
+// CHECK-INST: urshl { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0x3f,0xb2,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17eb23f <unknown>
+
+
+urshl {z0.s, z1.s}, {z0.s, z1.s}, z0.s // 11000001-10100000-10100010-00100001
+// CHECK-INST: urshl { z0.s, z1.s }, { z0.s, z1.s }, z0.s
+// CHECK-ENCODING: [0x21,0xa2,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0a221 <unknown>
+
+urshl {z20.s, z21.s}, {z20.s, z21.s}, z5.s // 11000001-10100101-10100010-00110101
+// CHECK-INST: urshl { z20.s, z21.s }, { z20.s, z21.s }, z5.s
+// CHECK-ENCODING: [0x35,0xa2,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5a235 <unknown>
+
+urshl {z22.s, z23.s}, {z22.s, z23.s}, z8.s // 11000001-10101000-10100010-00110111
+// CHECK-INST: urshl { z22.s, z23.s }, { z22.s, z23.s }, z8.s
+// CHECK-ENCODING: [0x37,0xa2,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8a237 <unknown>
+
+urshl {z30.s, z31.s}, {z30.s, z31.s}, z15.s // 11000001-10101111-10100010-00111111
+// CHECK-INST: urshl { z30.s, z31.s }, { z30.s, z31.s }, z15.s
+// CHECK-ENCODING: [0x3f,0xa2,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afa23f <unknown>
+
+
+urshl {z0.s, z1.s}, {z0.s, z1.s}, {z0.s, z1.s} // 11000001-10100000-10110010-00100001
+// CHECK-INST: urshl { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x21,0xb2,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0b221 <unknown>
+
+urshl {z20.s, z21.s}, {z20.s, z21.s}, {z20.s, z21.s} // 11000001-10110100-10110010-00110101
+// CHECK-INST: urshl { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }
+// CHECK-ENCODING: [0x35,0xb2,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4b235 <unknown>
+
+urshl {z22.s, z23.s}, {z22.s, z23.s}, {z8.s, z9.s} // 11000001-10101000-10110010-00110111
+// CHECK-INST: urshl { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }
+// CHECK-ENCODING: [0x37,0xb2,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8b237 <unknown>
+
+urshl {z30.s, z31.s}, {z30.s, z31.s}, {z30.s, z31.s} // 11000001-10111110-10110010-00111111
+// CHECK-INST: urshl { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0x3f,0xb2,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1beb23f <unknown>
+
+
+urshl {z0.d, z1.d}, {z0.d, z1.d}, z0.d // 11000001-11100000-10100010-00100001
+// CHECK-INST: urshl { z0.d, z1.d }, { z0.d, z1.d }, z0.d
+// CHECK-ENCODING: [0x21,0xa2,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0a221 <unknown>
+
+urshl {z20.d, z21.d}, {z20.d, z21.d}, z5.d // 11000001-11100101-10100010-00110101
+// CHECK-INST: urshl { z20.d, z21.d }, { z20.d, z21.d }, z5.d
+// CHECK-ENCODING: [0x35,0xa2,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5a235 <unknown>
+
+urshl {z22.d, z23.d}, {z22.d, z23.d}, z8.d // 11000001-11101000-10100010-00110111
+// CHECK-INST: urshl { z22.d, z23.d }, { z22.d, z23.d }, z8.d
+// CHECK-ENCODING: [0x37,0xa2,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8a237 <unknown>
+
+urshl {z30.d, z31.d}, {z30.d, z31.d}, z15.d // 11000001-11101111-10100010-00111111
+// CHECK-INST: urshl { z30.d, z31.d }, { z30.d, z31.d }, z15.d
+// CHECK-ENCODING: [0x3f,0xa2,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efa23f <unknown>
+
+
+urshl {z0.d, z1.d}, {z0.d, z1.d}, {z0.d, z1.d} // 11000001-11100000-10110010-00100001
+// CHECK-INST: urshl { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }
+// CHECK-ENCODING: [0x21,0xb2,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0b221 <unknown>
+
+urshl {z20.d, z21.d}, {z20.d, z21.d}, {z20.d, z21.d} // 11000001-11110100-10110010-00110101
+// CHECK-INST: urshl { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }
+// CHECK-ENCODING: [0x35,0xb2,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4b235 <unknown>
+
+urshl {z22.d, z23.d}, {z22.d, z23.d}, {z8.d, z9.d} // 11000001-11101000-10110010-00110111
+// CHECK-INST: urshl { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }
+// CHECK-ENCODING: [0x37,0xb2,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8b237 <unknown>
+
+urshl {z30.d, z31.d}, {z30.d, z31.d}, {z30.d, z31.d} // 11000001-11111110-10110010-00111111
+// CHECK-INST: urshl { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0x3f,0xb2,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1feb23f <unknown>
+
+
+urshl {z0.b, z1.b}, {z0.b, z1.b}, z0.b // 11000001-00100000-10100010-00100001
+// CHECK-INST: urshl { z0.b, z1.b }, { z0.b, z1.b }, z0.b
+// CHECK-ENCODING: [0x21,0xa2,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120a221 <unknown>
+
+urshl {z20.b, z21.b}, {z20.b, z21.b}, z5.b // 11000001-00100101-10100010-00110101
+// CHECK-INST: urshl { z20.b, z21.b }, { z20.b, z21.b }, z5.b
+// CHECK-ENCODING: [0x35,0xa2,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c125a235 <unknown>
+
+urshl {z22.b, z23.b}, {z22.b, z23.b}, z8.b // 11000001-00101000-10100010-00110111
+// CHECK-INST: urshl { z22.b, z23.b }, { z22.b, z23.b }, z8.b
+// CHECK-ENCODING: [0x37,0xa2,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128a237 <unknown>
+
+urshl {z30.b, z31.b}, {z30.b, z31.b}, z15.b // 11000001-00101111-10100010-00111111
+// CHECK-INST: urshl { z30.b, z31.b }, { z30.b, z31.b }, z15.b
+// CHECK-ENCODING: [0x3f,0xa2,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12fa23f <unknown>
+
+
+urshl {z0.b, z1.b}, {z0.b, z1.b}, {z0.b, z1.b} // 11000001-00100000-10110010-00100001
+// CHECK-INST: urshl { z0.b, z1.b }, { z0.b, z1.b }, { z0.b, z1.b }
+// CHECK-ENCODING: [0x21,0xb2,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120b221 <unknown>
+
+urshl {z20.b, z21.b}, {z20.b, z21.b}, {z20.b, z21.b} // 11000001-00110100-10110010-00110101
+// CHECK-INST: urshl { z20.b, z21.b }, { z20.b, z21.b }, { z20.b, z21.b }
+// CHECK-ENCODING: [0x35,0xb2,0x34,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c134b235 <unknown>
+
+urshl {z22.b, z23.b}, {z22.b, z23.b}, {z8.b, z9.b} // 11000001-00101000-10110010-00110111
+// CHECK-INST: urshl { z22.b, z23.b }, { z22.b, z23.b }, { z8.b, z9.b }
+// CHECK-ENCODING: [0x37,0xb2,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128b237 <unknown>
+
+urshl {z30.b, z31.b}, {z30.b, z31.b}, {z30.b, z31.b} // 11000001-00111110-10110010-00111111
+// CHECK-INST: urshl { z30.b, z31.b }, { z30.b, z31.b }, { z30.b, z31.b }
+// CHECK-ENCODING: [0x3f,0xb2,0x3e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13eb23f <unknown>
+
+
+urshl {z0.h - z3.h}, {z0.h - z3.h}, z0.h // 11000001-01100000-10101010-00100001
+// CHECK-INST: urshl { z0.h - z3.h }, { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x21,0xaa,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160aa21 <unknown>
+
+urshl {z20.h - z23.h}, {z20.h - z23.h}, z5.h // 11000001-01100101-10101010-00110101
+// CHECK-INST: urshl { z20.h - z23.h }, { z20.h - z23.h }, z5.h
+// CHECK-ENCODING: [0x35,0xaa,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165aa35 <unknown>
+
+urshl {z20.h - z23.h}, {z20.h - z23.h}, z8.h // 11000001-01101000-10101010-00110101
+// CHECK-INST: urshl { z20.h - z23.h }, { z20.h - z23.h }, z8.h
+// CHECK-ENCODING: [0x35,0xaa,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168aa35 <unknown>
+
+urshl {z28.h - z31.h}, {z28.h - z31.h}, z15.h // 11000001-01101111-10101010-00111101
+// CHECK-INST: urshl { z28.h - z31.h }, { z28.h - z31.h }, z15.h
+// CHECK-ENCODING: [0x3d,0xaa,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16faa3d <unknown>
+
+
+urshl {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h} // 11000001-01100000-10111010-00100001
+// CHECK-INST: urshl { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x21,0xba,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160ba21 <unknown>
+
+urshl {z20.h - z23.h}, {z20.h - z23.h}, {z20.h - z23.h} // 11000001-01110100-10111010-00110101
+// CHECK-INST: urshl { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x35,0xba,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174ba35 <unknown>
+
+urshl {z20.h - z23.h}, {z20.h - z23.h}, {z8.h - z11.h} // 11000001-01101000-10111010-00110101
+// CHECK-INST: urshl { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x35,0xba,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168ba35 <unknown>
+
+urshl {z28.h - z31.h}, {z28.h - z31.h}, {z28.h - z31.h} // 11000001-01111100-10111010-00111101
+// CHECK-INST: urshl { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x3d,0xba,0x7c,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17cba3d <unknown>
+
+
+urshl {z0.s - z3.s}, {z0.s - z3.s}, z0.s // 11000001-10100000-10101010-00100001
+// CHECK-INST: urshl { z0.s - z3.s }, { z0.s - z3.s }, z0.s
+// CHECK-ENCODING: [0x21,0xaa,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0aa21 <unknown>
+
+urshl {z20.s - z23.s}, {z20.s - z23.s}, z5.s // 11000001-10100101-10101010-00110101
+// CHECK-INST: urshl { z20.s - z23.s }, { z20.s - z23.s }, z5.s
+// CHECK-ENCODING: [0x35,0xaa,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5aa35 <unknown>
+
+urshl {z20.s - z23.s}, {z20.s - z23.s}, z8.s // 11000001-10101000-10101010-00110101
+// CHECK-INST: urshl { z20.s - z23.s }, { z20.s - z23.s }, z8.s
+// CHECK-ENCODING: [0x35,0xaa,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8aa35 <unknown>
+
+urshl {z28.s - z31.s}, {z28.s - z31.s}, z15.s // 11000001-10101111-10101010-00111101
+// CHECK-INST: urshl { z28.s - z31.s }, { z28.s - z31.s }, z15.s
+// CHECK-ENCODING: [0x3d,0xaa,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afaa3d <unknown>
+
+
+urshl {z0.s - z3.s}, {z0.s - z3.s}, {z0.s - z3.s} // 11000001-10100000-10111010-00100001
+// CHECK-INST: urshl { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x21,0xba,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0ba21 <unknown>
+
+urshl {z20.s - z23.s}, {z20.s - z23.s}, {z20.s - z23.s} // 11000001-10110100-10111010-00110101
+// CHECK-INST: urshl { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }
+// CHECK-ENCODING: [0x35,0xba,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4ba35 <unknown>
+
+urshl {z20.s - z23.s}, {z20.s - z23.s}, {z8.s - z11.s} // 11000001-10101000-10111010-00110101
+// CHECK-INST: urshl { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x35,0xba,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8ba35 <unknown>
+
+urshl {z28.s - z31.s}, {z28.s - z31.s}, {z28.s - z31.s} // 11000001-10111100-10111010-00111101
+// CHECK-INST: urshl { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x3d,0xba,0xbc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bcba3d <unknown>
+
+
+urshl {z0.d - z3.d}, {z0.d - z3.d}, z0.d // 11000001-11100000-10101010-00100001
+// CHECK-INST: urshl { z0.d - z3.d }, { z0.d - z3.d }, z0.d
+// CHECK-ENCODING: [0x21,0xaa,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0aa21 <unknown>
+
+urshl {z20.d - z23.d}, {z20.d - z23.d}, z5.d // 11000001-11100101-10101010-00110101
+// CHECK-INST: urshl { z20.d - z23.d }, { z20.d - z23.d }, z5.d
+// CHECK-ENCODING: [0x35,0xaa,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5aa35 <unknown>
+
+urshl {z20.d - z23.d}, {z20.d - z23.d}, z8.d // 11000001-11101000-10101010-00110101
+// CHECK-INST: urshl { z20.d - z23.d }, { z20.d - z23.d }, z8.d
+// CHECK-ENCODING: [0x35,0xaa,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8aa35 <unknown>
+
+urshl {z28.d - z31.d}, {z28.d - z31.d}, z15.d // 11000001-11101111-10101010-00111101
+// CHECK-INST: urshl { z28.d - z31.d }, { z28.d - z31.d }, z15.d
+// CHECK-ENCODING: [0x3d,0xaa,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efaa3d <unknown>
+
+
+urshl {z0.d - z3.d}, {z0.d - z3.d}, {z0.d - z3.d} // 11000001-11100000-10111010-00100001
+// CHECK-INST: urshl { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x21,0xba,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0ba21 <unknown>
+
+urshl {z20.d - z23.d}, {z20.d - z23.d}, {z20.d - z23.d} // 11000001-11110100-10111010-00110101
+// CHECK-INST: urshl { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x35,0xba,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4ba35 <unknown>
+
+urshl {z20.d - z23.d}, {z20.d - z23.d}, {z8.d - z11.d} // 11000001-11101000-10111010-00110101
+// CHECK-INST: urshl { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x35,0xba,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8ba35 <unknown>
+
+urshl {z28.d - z31.d}, {z28.d - z31.d}, {z28.d - z31.d} // 11000001-11111100-10111010-00111101
+// CHECK-INST: urshl { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x3d,0xba,0xfc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fcba3d <unknown>
+
+
+urshl {z0.b - z3.b}, {z0.b - z3.b}, z0.b // 11000001-00100000-10101010-00100001
+// CHECK-INST: urshl { z0.b - z3.b }, { z0.b - z3.b }, z0.b
+// CHECK-ENCODING: [0x21,0xaa,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120aa21 <unknown>
+
+urshl {z20.b - z23.b}, {z20.b - z23.b}, z5.b // 11000001-00100101-10101010-00110101
+// CHECK-INST: urshl { z20.b - z23.b }, { z20.b - z23.b }, z5.b
+// CHECK-ENCODING: [0x35,0xaa,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c125aa35 <unknown>
+
+urshl {z20.b - z23.b}, {z20.b - z23.b}, z8.b // 11000001-00101000-10101010-00110101
+// CHECK-INST: urshl { z20.b - z23.b }, { z20.b - z23.b }, z8.b
+// CHECK-ENCODING: [0x35,0xaa,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128aa35 <unknown>
+
+urshl {z28.b - z31.b}, {z28.b - z31.b}, z15.b // 11000001-00101111-10101010-00111101
+// CHECK-INST: urshl { z28.b - z31.b }, { z28.b - z31.b }, z15.b
+// CHECK-ENCODING: [0x3d,0xaa,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12faa3d <unknown>
+
+
+urshl {z0.b - z3.b}, {z0.b - z3.b}, {z0.b - z3.b} // 11000001-00100000-10111010-00100001
+// CHECK-INST: urshl { z0.b - z3.b }, { z0.b - z3.b }, { z0.b - z3.b }
+// CHECK-ENCODING: [0x21,0xba,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120ba21 <unknown>
+
+urshl {z20.b - z23.b}, {z20.b - z23.b}, {z20.b - z23.b} // 11000001-00110100-10111010-00110101
+// CHECK-INST: urshl { z20.b - z23.b }, { z20.b - z23.b }, { z20.b - z23.b }
+// CHECK-ENCODING: [0x35,0xba,0x34,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c134ba35 <unknown>
+
+urshl {z20.b - z23.b}, {z20.b - z23.b}, {z8.b - z11.b} // 11000001-00101000-10111010-00110101
+// CHECK-INST: urshl { z20.b - z23.b }, { z20.b - z23.b }, { z8.b - z11.b }
+// CHECK-ENCODING: [0x35,0xba,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128ba35 <unknown>
+
+urshl {z28.b - z31.b}, {z28.b - z31.b}, {z28.b - z31.b} // 11000001-00111100-10111010-00111101
+// CHECK-INST: urshl { z28.b - z31.b }, { z28.b - z31.b }, { z28.b - z31.b }
+// CHECK-ENCODING: [0x3d,0xba,0x3c,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13cba3d <unknown>
+
+
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