[llvm] 223f466 - [RISCV] Add ORI to hasAllNBitUsers.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-10-24T21:33:17-07:00
New Revision: 223f466f4f39f052196e2883222666e5f2b8a01e

URL: https://github.com/llvm/llvm-project/commit/223f466f4f39f052196e2883222666e5f2b8a01e
DIFF: https://github.com/llvm/llvm-project/commit/223f466f4f39f052196e2883222666e5f2b8a01e.diff

LOG: [RISCV] Add ORI to hasAllNBitUsers.

If the immediate is negative with sufficient leading ones, then
the upper bits of the other operand aren't demanded.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    llvm/test/CodeGen/RISCV/mul.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index e33bcc5e04e2c..9144f57beffd7 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2304,6 +2304,12 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits) const {
       if (Bits < (64 - countLeadingZeros(User->getConstantOperandVal(1))))
         return false;
       break;
+    case RISCV::ORI: {
+      uint64_t Imm = cast<ConstantSDNode>(User->getOperand(1))->getSExtValue();
+      if (Bits < (64 - countLeadingOnes(Imm)))
+        return false;
+      break;
+    }
     case RISCV::SEXT_B:
       if (Bits < 8)
         return false;

diff  --git a/llvm/test/CodeGen/RISCV/mul.ll b/llvm/test/CodeGen/RISCV/mul.ll
index 3923c4340d30e..e30e5e69b8464 100644
--- a/llvm/test/CodeGen/RISCV/mul.ll
+++ b/llvm/test/CodeGen/RISCV/mul.ll
@@ -1589,3 +1589,71 @@ define i8 @mulsub_demand(i8 %x, i8 %y) nounwind {
   %r = and i8 %a, 15
   ret i8 %r
 }
+
+define i8 @muladd_demand_2(i8 %x, i8 %y) nounwind {
+; RV32I-LABEL: muladd_demand_2:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    slli a0, a0, 1
+; RV32I-NEXT:    sub a0, a1, a0
+; RV32I-NEXT:    ori a0, a0, -16
+; RV32I-NEXT:    ret
+;
+; RV32IM-LABEL: muladd_demand_2:
+; RV32IM:       # %bb.0:
+; RV32IM-NEXT:    slli a0, a0, 1
+; RV32IM-NEXT:    sub a0, a1, a0
+; RV32IM-NEXT:    ori a0, a0, -16
+; RV32IM-NEXT:    ret
+;
+; RV64I-LABEL: muladd_demand_2:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slliw a0, a0, 1
+; RV64I-NEXT:    subw a0, a1, a0
+; RV64I-NEXT:    ori a0, a0, -16
+; RV64I-NEXT:    ret
+;
+; RV64IM-LABEL: muladd_demand_2:
+; RV64IM:       # %bb.0:
+; RV64IM-NEXT:    slliw a0, a0, 1
+; RV64IM-NEXT:    subw a0, a1, a0
+; RV64IM-NEXT:    ori a0, a0, -16
+; RV64IM-NEXT:    ret
+  %m = mul i8 %x, 14
+  %a = add i8 %y, %m
+  %r = or i8 %a, 240
+  ret i8 %r
+}
+
+define i8 @mulsub_demand_2(i8 %x, i8 %y) nounwind {
+; RV32I-LABEL: mulsub_demand_2:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    slli a0, a0, 1
+; RV32I-NEXT:    add a0, a1, a0
+; RV32I-NEXT:    ori a0, a0, -16
+; RV32I-NEXT:    ret
+;
+; RV32IM-LABEL: mulsub_demand_2:
+; RV32IM:       # %bb.0:
+; RV32IM-NEXT:    slli a0, a0, 1
+; RV32IM-NEXT:    add a0, a1, a0
+; RV32IM-NEXT:    ori a0, a0, -16
+; RV32IM-NEXT:    ret
+;
+; RV64I-LABEL: mulsub_demand_2:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slliw a0, a0, 1
+; RV64I-NEXT:    addw a0, a1, a0
+; RV64I-NEXT:    ori a0, a0, -16
+; RV64I-NEXT:    ret
+;
+; RV64IM-LABEL: mulsub_demand_2:
+; RV64IM:       # %bb.0:
+; RV64IM-NEXT:    slliw a0, a0, 1
+; RV64IM-NEXT:    addw a0, a1, a0
+; RV64IM-NEXT:    ori a0, a0, -16
+; RV64IM-NEXT:    ret
+  %m = mul i8 %x, 14
+  %a = sub i8 %y, %m
+  %r = or i8 %a, 240
+  ret i8 %r
+}