[PATCH] D135599: [AArch64]SME2 Single and multiple vectors SVE Destructive two/four registers[part2]

[Caroline via Phabricator via llvm-commits]

CarolineConcatto marked an inline comment as done.
CarolineConcatto added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td:376
+defm SMAX_VG2_2Z2Z : sme2_int_sve_destructive_vector_vg2_multi<"smax",  0b000000>;
+defm SMAX_VG4_4Z2Z : sme2_int_sve_destructive_vector_vg4_multi<"smax",  0b000000>;
+
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paulwalker-arm wrote:
> Should this be `SMAX_VG4_4Z4Z`? If yes then you'll need to check all new defs in this patch because I've seen this potentially incorrect naming several times.
> 
> Whilst mentioning consistency the choice of whether to use `_VG#` seems arbitrary or perhaps I'm misinterpreting it's meaning.  For example `SRSHL_2Z2Z` looks like it should have `_VG2` but doesn't.  That said, given we specify the register types within the instructions (i.e. _2Z2Z) I'm wondering if most all the `_VG#` usages are redundant?
> 
> Redundancy is likely a question for later but I do think you should be naming the instructions consistently.
I agree that the naming needs to be consistent. I missed that.
Thank you for noticing. I will double-check the following patches for name consistency.


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