[llvm] c782a93 - [Instcombine] Add coverage for demanded bits of insertelement

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2022-10-24T13:17:33-07:00
New Revision: c782a937739cf7d503687e5374a8832a8a3ab4ef

URL: https://github.com/llvm/llvm-project/commit/c782a937739cf7d503687e5374a8832a8a3ab4ef
DIFF: https://github.com/llvm/llvm-project/commit/c782a937739cf7d503687e5374a8832a8a3ab4ef.diff

LOG: [Instcombine] Add coverage for demanded bits of insertelement

Added: 
    llvm/test/Transforms/InstCombine/insertelement.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/InstCombine/insertelement.ll b/llvm/test/Transforms/InstCombine/insertelement.ll
new file mode 100644
index 000000000000..976c495465ce
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/insertelement.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -passes=instcombine -S | FileCheck %s
+
+define <4 x i32> @insert_known_idx(<4 x i32> %x) {
+; CHECK-LABEL: @insert_known_idx(
+; CHECK-NEXT:    [[V1:%.*]] = and <4 x i32> [[X:%.*]], <i32 poison, i32 7, i32 7, i32 7>
+; CHECK-NEXT:    [[V2:%.*]] = insertelement <4 x i32> [[V1]], i32 6, i64 0
+; CHECK-NEXT:    ret <4 x i32> [[V2]]
+;
+  %v1 = and <4 x i32> %x, <i32 7, i32 7, i32 7, i32 7>
+  %v2 = insertelement <4 x i32> %v1, i32 6, i32 0
+  %v3 = and <4 x i32> %v2, <i32 7, i32 7, i32 7, i32 7>
+  ret <4 x i32> %v3
+}
+
+define <4 x i32> @insert_unknown_idx(<4 x i32> %x, i32 %idx) {
+; CHECK-LABEL: @insert_unknown_idx(
+; CHECK-NEXT:    [[V1:%.*]] = and <4 x i32> [[X:%.*]], <i32 7, i32 7, i32 7, i32 7>
+; CHECK-NEXT:    [[V2:%.*]] = insertelement <4 x i32> [[V1]], i32 6, i32 [[IDX:%.*]]
+; CHECK-NEXT:    [[V3:%.*]] = and <4 x i32> [[V2]], <i32 7, i32 7, i32 7, i32 7>
+; CHECK-NEXT:    ret <4 x i32> [[V3]]
+;
+  %v1 = and <4 x i32> %x, <i32 7, i32 7, i32 7, i32 7>
+  %v2 = insertelement <4 x i32> %v1, i32 6, i32 %idx
+  %v3 = and <4 x i32> %v2, <i32 7, i32 7, i32 7, i32 7>
+  ret <4 x i32> %v3
+}