[PATCH] D135676: [AArch64]SME2 Multi-vector ternary indexed DOT and FMLA instructions

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:2073-2095
+multiclass sme2_fmla_array_vg2_index<string mnemonic, bits<4> opc> {
+  def NAME :  sme2_multi_vec_array_vg2_index_32b<opc{3}, opc{2-0}, ZZ_s_mul_r,
+                                               ZPR4b32, mnemonic>;
+
+  def : InstAlias<mnemonic # "\t$ZAda[$Rv, $imm3], $Zn, $Zm$i2",
+        (!cast<Instruction>(NAME) MatrixOp32:$ZAda,  MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7
+:$imm3, ZZ_s_mul_r:$Zn, ZPR4b32:$Zm, VectorIndexS:$i2), 0>;
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Rather than three classes can you create a single multiclass for `sme2_multi_vec_array_vg2_index_32b` of the same name that takes the same operands? If you're worried about the instruction alias, you should be able to use `ZPRRegOp:$Zm`.

This same comment likely applies to the other classes below.


================
Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:2074
+multiclass sme2_fmla_array_vg2_index<string mnemonic, bits<4> opc> {
+  def NAME :  sme2_multi_vec_array_vg2_index_32b<opc{3}, opc{2-0}, ZZ_s_mul_r,
+                                               ZPR4b32, mnemonic>;
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You may as well just pass in `opc` untouched and do the split within `sme2_multi_vec_array_vg2_index_32b`.


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  https://reviews.llvm.org/D135676/new/

https://reviews.llvm.org/D135676