[llvm] 718bb22 - [AArch64][PAC] Select XPAC for ptrauth.strip intrinsic.

[Ahmed Bougacha via llvm-commits]

Author: Ahmed Bougacha
Date: 2022-10-24T08:15:56-07:00
New Revision: 718bb22c28064ec6c6d9a7c9a36be1b1e9a64316

URL: https://github.com/llvm/llvm-project/commit/718bb22c28064ec6c6d9a7c9a36be1b1e9a64316
DIFF: https://github.com/llvm/llvm-project/commit/718bb22c28064ec6c6d9a7c9a36be1b1e9a64316.diff

LOG: [AArch64][PAC] Select XPAC for ptrauth.strip intrinsic.

Differential Revision: https://reviews.llvm.org/D132385

Added: 
    llvm/test/CodeGen/AArch64/ptrauth-intrinsic-strip.ll

Modified: 
    llvm/lib/Target/AArch64/AArch64InstrInfo.td
    llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 3d439a276597..46c935634f8b 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -1361,7 +1361,12 @@ let Predicates = [HasPAuth] in {
   defm AUT : SignAuth<0b001, 0b011, "aut", null_frag>;
 
   def XPACI : ClearAuth<0, "xpaci">;
+  def : Pat<(int_ptrauth_strip GPR64:$Rd, 0), (XPACI GPR64:$Rd)>;
+  def : Pat<(int_ptrauth_strip GPR64:$Rd, 1), (XPACI GPR64:$Rd)>;
+
   def XPACD : ClearAuth<1, "xpacd">;
+  def : Pat<(int_ptrauth_strip GPR64:$Rd, 2), (XPACD GPR64:$Rd)>;
+  def : Pat<(int_ptrauth_strip GPR64:$Rd, 3), (XPACD GPR64:$Rd)>;
 
   def PACGA : SignAuthTwoOperand<0b1100, "pacga", int_ptrauth_sign_generic>;
 

diff  --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index 88c560cafffb..14fac54776c9 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -5864,6 +5864,22 @@ bool AArch64InstructionSelector::selectIntrinsic(MachineInstr &I,
     I.eraseFromParent();
     return true;
   }
+  case Intrinsic::ptrauth_strip: {
+    Register DstReg = I.getOperand(0).getReg();
+    Register ValReg = I.getOperand(2).getReg();
+    uint64_t Key = I.getOperand(3).getImm();
+
+    if (Key > AArch64PACKey::LAST)
+      return false;
+    unsigned Opcode = getXPACOpcodeForKey((AArch64PACKey::ID)Key);
+
+    MIB.buildInstr(Opcode, {DstReg}, {ValReg});
+
+    RBI.constrainGenericRegister(DstReg, AArch64::GPR64RegClass, MRI);
+    RBI.constrainGenericRegister(ValReg, AArch64::GPR64RegClass, MRI);
+    I.eraseFromParent();
+    return true;
+  }
   case Intrinsic::frameaddress:
   case Intrinsic::returnaddress: {
     MachineFunction &MF = *I.getParent()->getParent();

diff  --git a/llvm/test/CodeGen/AArch64/ptrauth-intrinsic-strip.ll b/llvm/test/CodeGen/AArch64/ptrauth-intrinsic-strip.ll
new file mode 100644
index 000000000000..a99c046a8955
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/ptrauth-intrinsic-strip.ll
@@ -0,0 +1,43 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple arm64e-apple-darwin -verify-machineinstrs -global-isel=0 | FileCheck %s
+; RUN: llc < %s -mtriple arm64e-apple-darwin -verify-machineinstrs -global-isel=1 -global-isel-abort=1 | FileCheck %s
+
+target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+
+define i64 @test_strip_ia(i64 %arg) {
+; CHECK-LABEL: test_strip_ia:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    xpaci x0
+; CHECK-NEXT:    ret
+  %tmp = call i64 @llvm.ptrauth.strip(i64 %arg, i32 0)
+  ret i64 %tmp
+}
+
+define i64 @test_strip_ib(i64 %arg) {
+; CHECK-LABEL: test_strip_ib:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    xpaci x0
+; CHECK-NEXT:    ret
+  %tmp = call i64 @llvm.ptrauth.strip(i64 %arg, i32 1)
+  ret i64 %tmp
+}
+
+define i64 @test_strip_da(i64 %arg) {
+; CHECK-LABEL: test_strip_da:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    xpacd x0
+; CHECK-NEXT:    ret
+  %tmp = call i64 @llvm.ptrauth.strip(i64 %arg, i32 2)
+  ret i64 %tmp
+}
+
+define i64 @test_strip_db(i64 %arg) {
+; CHECK-LABEL: test_strip_db:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    xpacd x0
+; CHECK-NEXT:    ret
+  %tmp = call i64 @llvm.ptrauth.strip(i64 %arg, i32 3)
+  ret i64 %tmp
+}
+
+declare i64 @llvm.ptrauth.strip(i64, i32)