[PATCH] D136587: use riscv vsetvl to tailfolding

[Philip Reames via Phabricator via llvm-commits]

reames added a subscriber: simoll.
reames added a comment.

FYI, this isn't going to be accepted in the current form.  We don't allow the use of target specific intrinsics directly from the generic IR optimizer.

If you're interested in this approach, I recommend you take a look at the work that BSC has done using the VP intrinsics.  I think that's the closest we have to something which is likely to eventually make it upstream.   If you wanted to spend time working on that, you should talk to @simoll, and come to the next RISC-V sync up call or VP sync up.  (The VP syncs have been getting canceled, so the general RISC-V sync is probably a better idea.)  I'd also be happy to jump on a call and talk through this topic.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136587/new/

https://reviews.llvm.org/D136587