[PATCH] D135601: [AArch64]SME2 Multiple vectors Int/FP clamp instructions for two/four registers

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm accepted this revision.
paulwalker-arm added a comment.
This revision is now accepted and ready to land.

Happy as is but I offer some advice that I think means supporting ZIP and UZP would just require a couple if extra lines plus some tests.



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Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:2011
+multiclass sme2_int_clamp_vector_vg2_multi<string mnemonic, bit u>{
+  def _B : sme2_clamp_vector_vg2_multi<0b00, 0b01, u, ZZ_b_mul_r, ZPR8, mnemonic>;
+  def _H : sme2_clamp_vector_vg2_multi<0b01, 0b01, u, ZZ_h_mul_r, ZPR16, mnemonic>;
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A bit like with D135599, you'll be better placed passing this into here as a single opcode (along with inst{12}. Doing this means you can reuse the same class for "SME2 multi-vec ZIP two registers" that also sits within this encoding group.


Repository:
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  https://reviews.llvm.org/D135601/new/

https://reviews.llvm.org/D135601