[PATCH] D136158: [AArch64] Adjust operand sequence for Add+Sub to combine more inline shift

chenglin.bi via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Oct 24 01:37:50 PDT 2022


bcl5980 added a comment.

In D136158#3878602 <https://reviews.llvm.org/D136158#3878602>, @dmgreen wrote:

> Have you tried testing this? I think it will get stuck in DAG combines.
>
> Otherwise the idea sounds good. Have you considered doing it for GlobalISel, or in a way that GlobalISel would also benefit?

I haven't found any stuck in DAG combine local and it looks all of the premerge test is also passed:
https://reviews.llvm.org/harbormaster/build/291788/

Which combination do you think will cause the dead loop in DAG combine with this patch? I can try to create a test for that.

I can try to do it in GISel also in another patch later.


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