[PATCH] D136525: [M68k] Add codegen pattern for atomic load / store

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0x59616e added a comment.

In D136525#3877522 <https://reviews.llvm.org/D136525#3877522>, @nikic wrote:

> Preferably this should also include the implementation for atomic RMW/CAS instructions to prove that this lowering is legal. If native or at least kernel-supported CAS is not available, then atomic load/store needs to use libatomic (possibly subtarget dependent).
>
> It would also be good to include relevant quotes from the ISA manual -- atomicity of load/store is usually a given, but do they also guarantee a seq_cst ordering without a memory barrier?
>
> (Disclaimer: I'm not familiar with m68k, just covering the usual atomic lowering legality questions.)

Thanks for replying !

To be honest, I can find any word regarding the atomic ordering in the document. I can't find any memory barrier instruction either. I just follow what gcc does.

There is a discussion here: https://github.com/M680x0/M680x0-mono-repo/issues/13


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