[llvm] 913f08b - [DAG] Add freeze(sign/zero_extend_vector_inreg(x)) -> sign/zero_extend_vector_inreg(freeze(x)) folding

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2022-10-23T12:19:42+01:00
New Revision: 913f08b74c9ddb603658c5678ffc04d87cb64cf4

URL: https://github.com/llvm/llvm-project/commit/913f08b74c9ddb603658c5678ffc04d87cb64cf4
DIFF: https://github.com/llvm/llvm-project/commit/913f08b74c9ddb603658c5678ffc04d87cb64cf4.diff

LOG: [DAG] Add freeze(sign/zero_extend_vector_inreg(x)) -> sign/zero_extend_vector_inreg(freeze(x)) folding

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/test/CodeGen/X86/freeze-vector.ll

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index da02a2816f8a8..8967dab250db1 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -4638,6 +4638,8 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts,
   case ISD::ZERO_EXTEND:
   case ISD::TRUNCATE:
   case ISD::SIGN_EXTEND_INREG:
+  case ISD::SIGN_EXTEND_VECTOR_INREG:
+  case ISD::ZERO_EXTEND_VECTOR_INREG:
   case ISD::BITCAST:
     return false;
 

diff  --git a/llvm/test/CodeGen/X86/freeze-vector.ll b/llvm/test/CodeGen/X86/freeze-vector.ll
index fe7d30c3e5970..ff90ba39d9621 100644
--- a/llvm/test/CodeGen/X86/freeze-vector.ll
+++ b/llvm/test/CodeGen/X86/freeze-vector.ll
@@ -16,8 +16,7 @@ define <4 x i32> @freeze_insert_subvector(<8 x i32> %a0) nounwind {
 define <2 x i64> @freeze_sign_extend_vector_inreg(<16 x i8> %a0) nounwind {
 ; CHECK-LABEL: freeze_sign_extend_vector_inreg:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vpmovsxbd %xmm0, %xmm0
-; CHECK-NEXT:    vpmovsxdq %xmm0, %xmm0
+; CHECK-NEXT:    vpmovsxbq %xmm0, %xmm0
 ; CHECK-NEXT:    ret{{[l|q]}}
   %x = sext <16 x i8> %a0 to <16 x i32>
   %y = shufflevector <16 x i32> %x, <16 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
@@ -30,8 +29,7 @@ define <2 x i64> @freeze_sign_extend_vector_inreg(<16 x i8> %a0) nounwind {
 define <2 x i64> @freeze_zero_extend_vector_inreg(<16 x i8> %a0) nounwind {
 ; CHECK-LABEL: freeze_zero_extend_vector_inreg:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
-; CHECK-NEXT:    vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
+; CHECK-NEXT:    vpmovzxbq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero
 ; CHECK-NEXT:    ret{{[l|q]}}
   %x = zext <16 x i8> %a0 to <16 x i32>
   %y = shufflevector <16 x i32> %x, <16 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>