[PATCH] D136525: [M68k] Add codegen pattern for atomic load / store

[Nikita Popov via Phabricator via llvm-commits]

nikic added a comment.

Preferably this should also include the implementation for atomic RMW/CAS instructions to prove that this lowering is legal. If native or at least kernel-supported CAS is not available, then atomic load/store needs to use libatomic (possibly subtarget dependent).

It would also be good to include relevant quotes from the ISA manual -- atomicity of load/store is usually a given, but do they also guarantee a seq_cst ordering without a memory barrier?

(Disclaimer: I'm not familiar with m68k, just covering the usual atomic lowering legality questions.)


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https://reviews.llvm.org/D136525