[PATCH] D133399: [DAGCombiner] Fold (mul (sra X, BW-1), Y) -> (neg (and (sra X, BW-1), Y))

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/test/CodeGen/AMDGPU/mad_64_32.ll:192
 ; SI-NEXT:    v_ashrrev_i32_e32 v7, 31, v1
-; SI-NEXT:    v_mul_hi_u32 v14, v6, v1
-; SI-NEXT:    v_mul_lo_u32 v13, v0, v7
-; SI-NEXT:    v_mul_hi_u32 v10, v0, v7
-; SI-NEXT:    v_add_i32_e32 v12, vcc, v11, v12
-; SI-NEXT:    v_addc_u32_e32 v14, vcc, 0, v14, vcc
-; SI-NEXT:    v_mul_hi_u32 v8, v6, v7
-; SI-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
-; SI-NEXT:    v_addc_u32_e32 v10, vcc, 0, v10, vcc
-; SI-NEXT:    v_mul_i32_i24_e32 v9, v6, v7
-; SI-NEXT:    v_add_i32_e32 v10, vcc, v14, v10
-; SI-NEXT:    v_mul_hi_i32 v6, v1, v6
-; SI-NEXT:    v_mul_hi_i32 v7, v7, v0
-; SI-NEXT:    v_addc_u32_e64 v14, s[4:5], 0, 0, vcc
-; SI-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; SI-NEXT:    v_addc_u32_e32 v8, vcc, v8, v14, vcc
-; SI-NEXT:    v_add_i32_e32 v10, vcc, v13, v11
+; SI-NEXT:    v_and_b32_e32 v9, v6, v1
+; SI-NEXT:    v_and_b32_e32 v10, v7, v0
----------------
craig.topper wrote:
> @arsenm @foad on some build bots this v_and_b32_e32 and the one after it seem to be in a different order. Any idea what could be going on?
> 
> Failing example https://lab.llvm.org/buildbot/#/builders/58/builds/27599/steps/6/logs/FAIL__LLVM__mad_64_32_ll
No idea. I'd guess nondeterminism somewhere else


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https://reviews.llvm.org/D133399